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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id 207sm543411pfz.203.2020.08.04.18.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Aug 2020 18:47:55 -0700 (PDT) Date: Tue, 04 Aug 2020 18:47:55 -0700 (PDT) X-Google-Original-Date: Tue, 04 Aug 2020 18:41:10 PDT (-0700) Subject: Re: [PATCH v6 4/4] dt-bindings: timer: Add CLINT bindings In-Reply-To: <20200724071822.126758-5-anup.patel@wdc.com> CC: Paul Walmsley , aou@eecs.berkeley.edu, robh+dt@kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, Damien Le Moal , Atish Patra , Alistair Francis , anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , kernel@esmil.dk From: Palmer Dabbelt To: Anup Patel Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, 24 Jul 2020 00:18:22 PDT (-0700), Anup Patel wrote: > We add DT bindings documentation for CLINT device. > > Signed-off-by: Anup Patel > Reviewed-by: Palmer Dabbelt > Tested-by: Emil Renner Berhing > --- > .../bindings/timer/sifive,clint.yaml | 60 +++++++++++++++++++ > 1 file changed, 60 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > new file mode 100644 > index 000000000000..2a0e9cd9fbcf > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -0,0 +1,60 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive Core Local Interruptor > + > +maintainers: > + - Palmer Dabbelt > + - Anup Patel > + > +description: > + SiFive (and other RISC-V) SOCs include an implementation of the SiFive > + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor > + interrupts. It directly connects to the timer and inter-processor interrupt > + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local > + interrupt controller is the parent interrupt controller for CLINT device. > + The clock frequency of CLINT is specified via "timebase-frequency" DT > + property of "/cpus" DT node. The "timebase-frequency" DT property is > + described in Documentation/devicetree/bindings/riscv/cpus.yaml > + > +properties: > + compatible: > + items: > + - const: sifive,fu540-c000-clint > + - const: sifive,clint0 > + > + description: > + Should be "sifive,-clint" and "sifive,clint". > + Supported compatible strings are - > + "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated > + onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive > + CLINT v0 IP block with no chip integration tweaks. > + Please refer to sifive-blocks-ip-versioning.txt for details Perfect! I was going to mention that we forgot to define the "sifive,${name}${version}" scheme but I guess I just forgot that we did define it ;) > + > + reg: > + maxItems: 1 > + > + interrupts-extended: > + minItems: 1 > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts-extended > + > +examples: > + - | > + timer@2000000 { > + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; > + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 > + &cpu2intc 3 &cpu2intc 7 > + &cpu3intc 3 &cpu3intc 7 > + &cpu4intc 3 &cpu4intc 7>; > + reg = <0x2000000 0x10000>; > + }; > +... Reviewed-by: Palmer Dabbelt