From: Bhupesh Sharma <bhsharma@redhat.com>
To: linux-kernel@vger.kernel.org
Cc: bhsharma@redhat.com, bhupesh.linux@gmail.com, x86@kernel.org,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
kexec@lists.infradead.org, James Morse <james.morse@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Will Deacon <will@kernel.org>,
Steve Capper <steve.capper@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Dave Anderson <anderson@redhat.com>,
Kazuhito Hagio <k-hagio@ab.jp.nec.com>
Subject: [RESEND PATCH v5 5/5] Documentation/vmcoreinfo: Add documentation for 'TCR_EL1.T1SZ'
Date: Sat, 30 Nov 2019 01:29:19 +0530 [thread overview]
Message-ID: <1575057559-25496-6-git-send-email-bhsharma@redhat.com> (raw)
In-Reply-To: <1575057559-25496-1-git-send-email-bhsharma@redhat.com>
Add documentation for TCR_EL1.T1SZ variable being added to
vmcoreinfo.
It indicates the size offset of the memory region addressed by TTBR1_EL1
and hence can be used for determining the vabits_actual value.
Cc: James Morse <james.morse@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Steve Capper <steve.capper@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Dave Anderson <anderson@redhat.com>
Cc: Kazuhito Hagio <k-hagio@ab.jp.nec.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: kexec@lists.infradead.org
Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
---
Documentation/admin-guide/kdump/vmcoreinfo.rst | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst b/Documentation/admin-guide/kdump/vmcoreinfo.rst
index 447b64314f56..f9349f9d3345 100644
--- a/Documentation/admin-guide/kdump/vmcoreinfo.rst
+++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst
@@ -398,6 +398,12 @@ KERNELOFFSET
The kernel randomization offset. Used to compute the page offset. If
KASLR is disabled, this value is zero.
+TCR_EL1.T1SZ
+------------
+
+Indicates the size offset of the memory region addressed by TTBR1_EL1
+and hence can be used for determining the vabits_actual value.
+
arm
===
--
2.7.4
next prev parent reply other threads:[~2019-11-29 19:59 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-29 19:59 [RESEND PATCH v5 0/5] Append new variables to vmcoreinfo (TCR_EL1.T1SZ for arm64 and MAX_PHYSMEM_BITS for all archs) Bhupesh Sharma
2019-11-29 19:59 ` [RESEND PATCH v5 1/5] crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo Bhupesh Sharma
2019-11-29 19:59 ` [RESEND PATCH v5 2/5] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Bhupesh Sharma
2019-12-12 10:32 ` James Morse
2019-12-25 19:01 ` Bhupesh Sharma
2020-01-10 18:39 ` James Morse
2020-01-10 19:00 ` Dave Anderson
2020-01-13 12:14 ` Bhupesh Sharma
2020-02-21 9:06 ` Amit Kachhap
2020-02-24 6:25 ` Bhupesh Sharma
2020-04-29 23:04 ` Scott Branden
2020-06-10 16:47 ` Bharat Gooty
2020-06-16 19:24 ` Bhupesh Sharma
2020-06-10 16:49 ` Bharat Gooty
2019-11-29 19:59 ` [RESEND PATCH v5 3/5] Documentation/arm64: Fix a simple typo in memory.rst Bhupesh Sharma
2019-11-29 19:59 ` [RESEND PATCH v5 4/5] Documentation/vmcoreinfo: Add documentation for 'MAX_PHYSMEM_BITS' Bhupesh Sharma
2019-11-29 19:59 ` Bhupesh Sharma [this message]
2019-12-12 10:32 ` [RESEND PATCH v5 5/5] Documentation/vmcoreinfo: Add documentation for 'TCR_EL1.T1SZ' James Morse
2019-12-25 18:49 ` Bhupesh Sharma
2020-06-03 18:47 ` Scott Branden
2020-06-03 20:38 ` Bhupesh Sharma
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