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From: Matthew Wilcox <willy@infradead.org>
To: "Paul E. McKenney" <paulmck@linux.ibm.com>
Cc: Andrea Parri <andrea.parri@amarulasolutions.com>,
	Will Deacon <will.deacon@arm.com>,
	corbet@lwn.net, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Arnd Bergmann <arnd@arndb.de>,
	David Laight <David.Laight@ACULAB.COM>,
	Alan Stern <stern@rowland.harvard.edu>,
	Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses
Date: Tue, 27 Nov 2018 11:22:34 -0800
Message-ID: <20181127192234.GF10377@bombadil.infradead.org> (raw)
In-Reply-To: <20181127184021.GS4170@linux.ibm.com>

On Tue, Nov 27, 2018 at 10:40:21AM -0800, Paul E. McKenney wrote:
> On Mon, Nov 26, 2018 at 08:33:49PM +0100, Andrea Parri wrote:
> > On Mon, Nov 26, 2018 at 04:52:14PM +0000, Will Deacon wrote:
> > > David Laight explains:
> > > 
> > >   | A long time ago there was a document from Intel that said that
> > >   | inb/outb weren't necessarily synchronised wrt memory accesses.
> > >   | (Might be P-pro era). However no processors actually behaved that
> > >   | way and more recent docs say that inb/outb are fully ordered.
> > 
> > No intention to diminish David Laight's authority of course, but I would
> > have really appreciated a reference to these "recent docs" (section, pg.
> > or the like, especially if a reference manual...) here...
> 
> I would be inclined to cut Will a break given the research for his
> recent talk on this topic, but it would be good to get an ack from
> someone from Intel.  And memory-model patches require an ack or better
> in any case.  ;-)

Here's a quote from Section 18.6 of volume 1 of the Software Developer
Manual, November 2018 edition:

When the I/O address space is used instead of memory-mapped I/O, the
situation is different in two respects:
• The processor never buffers I/O writes. Therefore, strict ordering of
I/O operations is enforced by the processor. (As with memory-mapped I/O,
it is possible for a chip set to post writes in certain I/O ranges.)
• The processor synchronizes I/O instruction execution with external
bus activity (see Table 18-1).

Table 18-1 says that in* delays execution of the current instruction until
completion of pending stores, and out* delays execution of the _next_
instruction until completion of both pending stores and the current store.

  reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-26 16:52 Will Deacon
2018-11-26 19:33 ` Andrea Parri
2018-11-27 18:40   ` Paul E. McKenney
2018-11-27 19:22     ` Matthew Wilcox [this message]
2018-11-26 19:42 ` Paul E. McKenney

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