From: Zong Li <zong.li@sifive.com>
To: corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, anup@brainfault.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH 2/2] Documentation/features: support gcov on RISC-V
Date: Thu, 2 Jan 2020 12:14:45 +0800 [thread overview]
Message-ID: <20200102041445.98195-3-zong.li@sifive.com> (raw)
In-Reply-To: <20200102041445.98195-1-zong.li@sifive.com>
Change status to "ok" for RISC-V architecture.
Lightly tested on QEMU and Hifive Unleashed board, seems to work as
expected.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt
index 059d58a549c7..6fb2b0671994 100644
--- a/Documentation/features/debug/gcov-profile-all/arch-support.txt
+++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt
@@ -23,7 +23,7 @@
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
- | riscv: | TODO |
+ | riscv: | ok |
| s390: | ok |
| sh: | ok |
| sparc: | TODO |
--
2.24.1
prev parent reply other threads:[~2020-01-02 4:14 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-02 4:14 [PATCH v2 0/2] Enable gcov for RISC-V Zong Li
2020-01-02 4:14 ` [PATCH 1/2] riscv: gcov: enable " Zong Li
2020-01-02 4:14 ` Zong Li [this message]
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