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From: Mike Leach <mike.leach@linaro.org>
To: mike.leach@linaro.org, linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org, coresight@lists.linaro.org,
	linux-doc@vger.kernel.org
Cc: linux-arm-msm@vger.kernel.org, mathieu.poirier@linaro.org,
	suzuki.poulose@arm.com, robh+dt@kernel.org, maxime@cerno.tech,
	liviu.dudau@arm.com, sudeep.holla@arm.com,
	lorenzo.pieralisi@arm.com, agross@kernel.org, corbet@lwn.net
Subject: [PATCH v8 10/15] dt-bindings: qcom: Add CTI options for qcom msm8916
Date: Mon, 13 Jan 2020 21:31:44 +0000
Message-ID: <20200113213149.25599-11-mike.leach@linaro.org> (raw)
In-Reply-To: <20200113213149.25599-1-mike.leach@linaro.org>

Adds system and CPU bound CTI definitions for Qualcom msm8916 platform
(Dragonboard DB410C).
System CTIs 2-11 are omitted as no information available at present.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++--
 1 file changed, 81 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 8686e101905c..68587968f5c0 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/arm/coresight-cti-dt.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -1357,7 +1358,7 @@
 			cpu = <&CPU3>;
 		};
 
-		etm@85c000 {
+		etm0: etm@85c000 {
 			compatible = "arm,coresight-etm4x", "arm,primecell";
 			reg = <0x85c000 0x1000>;
 
@@ -1375,7 +1376,7 @@
 			};
 		};
 
-		etm@85d000 {
+		etm1: etm@85d000 {
 			compatible = "arm,coresight-etm4x", "arm,primecell";
 			reg = <0x85d000 0x1000>;
 
@@ -1393,7 +1394,7 @@
 			};
 		};
 
-		etm@85e000 {
+		etm2: etm@85e000 {
 			compatible = "arm,coresight-etm4x", "arm,primecell";
 			reg = <0x85e000 0x1000>;
 
@@ -1411,7 +1412,7 @@
 			};
 		};
 
-		etm@85f000 {
+		etm3: etm@85f000 {
 			compatible = "arm,coresight-etm4x", "arm,primecell";
 			reg = <0x85f000 0x1000>;
 
@@ -1429,6 +1430,82 @@
 			};
 		};
 
+		/* System CTIs */
+		/* CTI 0 - TMC connections */
+		cti@810000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x810000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+		};
+
+		/* CTI 1 - TPIU connections */
+		cti@811000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x811000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+		};
+
+		/* CTIs 2-11 - no information - not instantiated */
+
+		/* Core CTIs; CTIs 12-15 */
+		/* CTI - CPU-0 */
+		cti@858000 {
+			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+				     "arm,primecell";
+			reg = <0x858000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU0>;
+			arm,cs-dev-assoc = <&etm0>;
+
+		};
+
+		/* CTI - CPU-1 */
+		cti@859000 {
+			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+				     "arm,primecell";
+			reg = <0x859000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU1>;
+			arm,cs-dev-assoc = <&etm1>;
+		};
+
+		/* CTI - CPU-2 */
+		cti@85a000 {
+			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+				     "arm,primecell";
+			reg = <0x85a000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU2>;
+			arm,cs-dev-assoc = <&etm2>;
+		};
+
+		/* CTI - CPU-3 */
+		cti@85b000 {
+			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+				     "arm,primecell";
+			reg = <0x85b000 0x1000>;
+
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+
+			cpu = <&CPU3>;
+			arm,cs-dev-assoc = <&etm3>;
+		};
+
+
 		venus: video-codec@1d00000 {
 			compatible = "qcom,msm8916-venus";
 			reg = <0x01d00000 0xff000>;
-- 
2.17.1


  parent reply index

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-13 21:31 [PATCH v8 00/15] CoreSight CTI Driver Mike Leach
2020-01-13 21:31 ` [PATCH v8 01/15] coresight: cti: Initial " Mike Leach
2020-01-13 21:31 ` [PATCH v8 02/15] coresight: cti: Add sysfs coresight mgmt reg access Mike Leach
2020-01-13 21:31 ` [PATCH v8 03/15] coresight: cti: Add sysfs access to program function regs Mike Leach
2020-01-13 21:31 ` [PATCH v8 04/15] coresight: cti: Add sysfs trigger / channel programming API Mike Leach
2020-01-15  9:42   ` Suzuki Kuruppassery Poulose
2020-01-13 21:31 ` [PATCH v8 05/15] dt-bindings: arm: Adds CoreSight CTI hardware definitions Mike Leach
2020-01-14 22:21   ` Rob Herring
2020-01-13 21:31 ` [PATCH v8 06/15] coresight: cti: Add device tree support for v8 arch CTI Mike Leach
2020-01-15  9:45   ` Suzuki Kuruppassery Poulose
2020-01-13 21:31 ` [PATCH v8 07/15] coresight: cti: Add device tree support for custom CTI Mike Leach
2020-01-15  9:55   ` Suzuki Kuruppassery Poulose
2020-01-13 21:31 ` [PATCH v8 08/15] coresight: cti: Enable CTI associated with devices Mike Leach
2020-01-15 11:14   ` Suzuki Kuruppassery Poulose
2020-01-28 19:32     ` Mike Leach
2020-01-13 21:31 ` [PATCH v8 09/15] coresight: cti: Add connection information to sysfs Mike Leach
2020-01-15 11:34   ` Suzuki Kuruppassery Poulose
2020-01-13 21:31 ` Mike Leach [this message]
2020-01-13 21:31 ` [PATCH v8 11/15] dt-bindings: arm: Juno platform - add CTI entries to device tree Mike Leach
2020-01-13 21:31 ` [PATCH v8 12/15] dt-bindings: hisilicon: Add CTI bindings for hi-6220 Mike Leach
2020-01-13 21:31 ` [PATCH v8 13/15] docs: coresight: Update documentation for CoreSight to cover CTI Mike Leach
2020-01-13 21:31 ` [PATCH v8 14/15] docs: sysfs: coresight: Add sysfs ABI documentation for CTI Mike Leach
2020-01-13 21:31 ` [PATCH v8 15/15] Update MAINTAINERS to add reviewer for CoreSight Mike Leach

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