arch/mips/pci/pci-ar2315.c:6: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst

[kernel test robot <lkp@intel.com>]

Hi Aditya,

FYI, the error/warning still remains.

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   1c23f9e627a7b412978b4e852793c5e3c3efc555
commit: 3e58e839150db0857dfcb3a0bb3d4af4c6ac1abf scripts: kernel-doc: add warning for comment not following kernel-doc syntax
date:   1 year, 5 months ago
config: mips-randconfig-r016-20220821 (https://download.01.org/0day-ci/archive/20220822/202208221854.8ASrzjKa-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3e58e839150db0857dfcb3a0bb3d4af4c6ac1abf
        git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
        git fetch --no-tags linus master
        git checkout 3e58e839150db0857dfcb3a0bb3d4af4c6ac1abf
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=mips SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> arch/mips/pci/pci-ar2315.c:6: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA


vim +6 arch/mips/pci/pci-ar2315.c

3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  @6   * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29   7   * and interrupt. PCI interface supports MMIO access method, but does not
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29   8   * seem to support I/O ports.
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29   9   *
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  10   * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  11   * a memory read/write command on the PCI bus. 30 LSBs of address on
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  12   * the bus are taken from memory read/write request and 2 MSBs are
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  13   * determined by PCI unit configuration.
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  14   *
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  15   * To work with the configuration space instead of memory is necessary set
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  16   * the CFG_SEL bit in the PCI_MISC_CONFIG register.
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  17   *
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  18   * Devices on the bus can perform DMA requests via chip BAR1. PCI host
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  19   * controller BARs are programmend as if an external device is programmed.
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  20   * Which means that during configuration, IDSEL pin of the chip should be
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  21   * asserted.
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  22   *
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  23   * We know (and support) only one board that uses the PCI interface -
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  24   * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  25   * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  26   * and IDSEL pin of AR2315 is connected to AD[16] line.
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  27   */
3ed7a2a702dc0f Sergey Ryazanov 2014-10-29  28  

:::::: The code at line 6 was first introduced by commit
:::::: 3ed7a2a702dc0f5bc44d67f27a1a289356b5dc42 MIPS: ath25: add AR2315 PCI host controller driver

:::::: TO: Sergey Ryazanov <ryazanov.s.a@gmail.com>
:::::: CC: Ralf Baechle <ralf@linux-mips.org>

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