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From: Alexander Graf <graf@amazon.com>
To: Jim Mattson <jmattson@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Jonathan Corbet <corbet@lwn.net>,
	Sean Christopherson <sean.j.christopherson@intel.com>,
	Vitaly Kuznetsov <vkuznets@redhat.com>,
	Wanpeng Li <wanpengli@tencent.com>,
	Joerg Roedel <joro@8bytes.org>,
	KarimAllah Raslan <karahmed@amazon.de>,
	kvm list <kvm@vger.kernel.org>, <linux-doc@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>,
	Aaron Lewis <aaronlewis@google.com>
Subject: Re: [PATCH v2 1/3] KVM: x86: Deflect unknown MSR accesses to user space
Date: Fri, 31 Jul 2020 13:42:22 +0200
Message-ID: <8d0bae24-c83d-df89-01cb-e52cddd8ba92@amazon.com> (raw)
In-Reply-To: <CALMp9eSSKra+Vic0U9kDeiT1y+Jfq6Vmrqsw+S8jqD0_oqH9zA@mail.gmail.com>



On 31.07.20 05:20, Jim Mattson wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you can confirm the sender and know the content is safe.
> 
> 
> 
> On Thu, Jul 30, 2020 at 4:53 PM Jim Mattson <jmattson@google.com> wrote:
>>
>> On Thu, Jul 30, 2020 at 4:08 PM Alexander Graf <graf@amazon.com> wrote:
>>> Do you have a particular situation in mind where that would not be the
>>> case and where we would still want to actually complete an MSR operation
>>> after the environment changed?
>>
>> As far as userspace is concerned, if it has replied with error=0, the
>> instruction has completed and retired. If the kernel executes a
>> different instruction at CS:RIP, the state is certainly inconsistent
>> for WRMSR exits. It would also be inconsistent for RDMSR exits if the
>> RDMSR emulation on the userspace side had any side-effects.
> 
> Actually, I think there's a potential problem with interrupt delivery
> even if the instruction bytes are the same. On the second pass, an
> interrupt could be delivered on the CS:IP of a WRMSR, even though
> userspace has already emulated the WRMSR instruction. This could be
> particularly awkward if the WRMSR was to the x2APIC TPR register, and
> in fact lowered the TPR sufficiently to allow a pending interrupt to
> be delivered.

Ok, you got me convinced here :). The following flow breaks with my model:

   * rdmsr on 0x123, traps to user space
   * user space handles it, writes data into run->msr
   * kernel injects pending IRQ
   * IRQ handler does rdmsr on 0x124, which would be handled by user space
   * kernel returns value for 0x123 to the read

So yes, I agree, we have to finish the instruction handling before we 
can go back into normal operation flow.


Alex



Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
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  reply index

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-29 23:59 [PATCH v2 0/3] Allow user space to restrict and augment MSR emulation Alexander Graf
2020-07-29 23:59 ` [PATCH v2 1/3] KVM: x86: Deflect unknown MSR accesses to user space Alexander Graf
2020-07-30  8:41   ` Vitaly Kuznetsov
2020-07-30 22:42   ` Jim Mattson
2020-07-30 23:07     ` Alexander Graf
2020-07-30 23:53       ` Jim Mattson
2020-07-31  3:20         ` Jim Mattson
2020-07-31 11:42           ` Alexander Graf [this message]
2020-07-29 23:59 ` [PATCH v2 2/3] KVM: x86: Introduce allow list for MSR emulation Alexander Graf
2020-07-30  8:59   ` Vitaly Kuznetsov
2020-07-31 11:59     ` Alexander Graf
2020-07-29 23:59 ` [PATCH v2 3/3] KVM: selftests: Add test for user space MSR handling Alexander Graf

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