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From: Bagas Sanjaya <bagasdotme@gmail.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>,
	linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org,
	dm-devel@redhat.com
Cc: ebiggers@kernel.org, elliott@hpe.com, gmazyland@gmail.com,
	luto@kernel.org, dave.hansen@linux.intel.com, tglx@linutronix.de,
	bp@alien8.de, mingo@kernel.org, x86@kernel.org,
	herbert@gondor.apana.org.au, ardb@kernel.org,
	dan.j.williams@intel.com, bernie.keany@intel.com,
	charishma1.gairuboyina@intel.com,
	lalithambika.krishnakumar@intel.com, nhuck@google.com,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	Jonathan Corbet <corbet@lwn.net>,
	linux-doc@vger.kernel.org
Subject: Re: [PATCH v8 01/12] Documentation/x86: Document Key Locker
Date: Mon, 5 Jun 2023 17:54:43 +0700	[thread overview]
Message-ID: <91fc8d61-1a34-bc37-41c1-1528ff93c654@gmail.com> (raw)
In-Reply-To: <20230603152227.12335-2-chang.seok.bae@intel.com>

On 6/3/23 22:22, Chang S. Bae wrote:
> +==============
> +x86 Key Locker
> +==============
> +
> +Introduction
> +============
> +
> +Key Locker is a CPU feature to reduce key exfiltration opportunities
> +while maintaining a programming interface similar to AES-NI. It
> +converts the AES key into an encoded form, called the 'key handle'.
> +The key handle is a wrapped version of the clear-text key where the
> +wrapping key has limited exposure. Once converted, all subsequent data
> +encryption using new AES instructions (AES-KL) uses this key handle,
> +reducing the exposure of private key material in memory.
> +
> +CPU-internal Wrapping Key
> +=========================
> +
> +The CPU-internal wrapping key is an entity in a software-invisible CPU
> +state. On every system boot, a new key is loaded. So the key handle that
> +was encoded by the old wrapping key is no longer usable on system shutdown
> +or reboot.
> +
> +And the key may be lost on the following exceptional situation upon wakeup:
> +
> +Wrapping Key Restore Failure
> +----------------------------
> +
> +The CPU state is volatile with the ACPI S3/4 sleep states. When the system
> +supports those states, the key has to be backed up so that it is restored
> +on wake up. The kernel saves the key in non-volatile media.
> +
> +The event of a wrapping key restore failure upon resume from suspend, all
> +established key handles become invalid. In flight dm-crypt operations
> +receive error results from pending operations. In the likely scenario that
> +dm-crypt is hosting the root filesystem the recovery is identical to if a
> +storage controller failed to resume from suspend, reboot. If the volume
"... resume from suspend or reboot."
> +impacted by a wrapping key restore failure is a data-volume then it is
> +possible that I/O errors on that volume do not bring down the rest of the
> +system. However, a reboot is still required because the kernel will have
> +soft-disabled Key Locker. Upon the failure, the crypto library code will
> +return -ENODEV on every AES-KL function call. The Key Locker implementation
> +only loads a new wrapping key at initial boot, not any time after like
> +resume from suspend.
> +
> +Use Case and Non-use Cases
> +==========================
> +
> +Bare metal disk encryption is the only intended use case.
> +
> +Userspace usage is not supported because there is no ABI provided to
> +communicate and coordinate wrapping-key restore failure to userspace. For
> +now, key restore failures are only coordinated with kernel users. But the
> +kernel can not prevent userspace from using the feature's AES instructions
> +('AES-KL') when the feature has been enabled. So, the lack of userspace
> +support is only documented, not actively enforced.
> +
> +Key Locker is not expected to be advertised to guest VMs and the kernel
> +implementation ignores it even if the VMM enumerates the capability. The
> +expectation is that a guest VM wants private wrapping key state, but the
> +architecture does not provide that. An emulation of that capability, by
> +caching per-VM wrapping keys in memory, defeats the purpose of Key Locker.
> +The backup / restore facility is also not performant enough to be suitable
> +for guest VM context switches.
> +
> +AES Instruction Set
> +===================
> +
> +The feature accompanies a new AES instruction set. This instruction set is
> +analogous to AES-NI. A set of AES-NI instructions can be mapped to an
> +AES-KL instruction. For example, AESENC128KL is responsible for ten rounds
> +of transformation, which is equivalent to nine times AESENC and one
> +AESENCLAST in AES-NI.
> +
> +But they have some notable differences:
> +
> +* AES-KL provides a secure data transformation using an encrypted key.
> +
> +* If an invalid key handle is provided, e.g. a corrupted one or a handle
> +  restriction failure, the instruction fails with setting RFLAGS.ZF. The
> +  crypto library implementation includes the flag check to return -EINVAL.
> +  Note that this flag is also set if the wrapping key is changed, e.g.,
> +  because of the backup error.
> +
> +* AES-KL implements support for 128-bit and 256-bit keys, but there is no
> +  AES-KL instruction to process an 192-bit key. The AES-KL cipher
> +  implementation logs a warning message with a 192-bit key and then falls
> +  back to AES-NI. So, this 192-bit key-size limitation is only documented,
> +  not enforced. It means the key will remain in clear-text in memory. This
> +  is to meet Linux crypto-cipher expectation that each implementation must
> +  support all the AES-compliant key sizes.
> +
> +* Some AES-KL hardware implementation may have noticeable performance
> +  overhead when compared with AES-NI instructions.
> +

The rest is LGTM, thanks!

Anyway,

Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com>

-- 
An old man doll... just what I always wanted! - Clara


  reply	other threads:[~2023-06-05 10:55 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20220112211258.21115-1-chang.seok.bae@intel.com>
2022-01-12 21:12 ` [PATCH v5 01/12] Documentation/x86: Document Key Locker Chang S. Bae
2023-06-05 10:52   ` Bagas Sanjaya
2022-01-12 21:12 ` [PATCH v5 09/12] x86/cpu: Add a configuration and command line option for " Chang S. Bae
     [not found] ` <20230410225936.8940-1-chang.seok.bae@intel.com>
2023-04-10 22:59   ` [PATCH v6 01/12] Documentation/x86: Document " Chang S. Bae
2023-04-10 22:59   ` [PATCH v6 09/12] x86/cpu: Add a configuration and command line option for " Chang S. Bae
     [not found]   ` <20230524165717.14062-1-chang.seok.bae@intel.com>
2023-05-24 16:57     ` [PATCH v7 01/12] Documentation/x86: Document " Chang S. Bae
2023-05-24 16:57     ` [PATCH v7 09/12] x86/cpu: Add a configuration and command line option for " Chang S. Bae
     [not found]     ` <20230603152227.12335-1-chang.seok.bae@intel.com>
2023-06-03 15:22       ` [PATCH v8 01/12] Documentation/x86: Document " Chang S. Bae
2023-06-05 10:54         ` Bagas Sanjaya [this message]
2023-06-06  2:17         ` Randy Dunlap
2023-06-06  4:18           ` Chang S. Bae
2023-06-03 15:22       ` [PATCH v8 09/12] x86/cpu: Add a configuration and command line option for " Chang S. Bae
2023-06-03 16:37         ` Borislav Petkov
2023-06-04 22:13           ` Chang S. Bae

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