From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F59DC433F5 for ; Sat, 18 Sep 2021 07:37:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5238061039 for ; Sat, 18 Sep 2021 07:37:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237629AbhIRHia (ORCPT ); Sat, 18 Sep 2021 03:38:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231351AbhIRHi2 (ORCPT ); Sat, 18 Sep 2021 03:38:28 -0400 Received: from mail-ua1-x931.google.com (mail-ua1-x931.google.com [IPv6:2607:f8b0:4864:20::931]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20894C061574; Sat, 18 Sep 2021 00:37:05 -0700 (PDT) Received: by mail-ua1-x931.google.com with SMTP id v9so7572570uak.1; Sat, 18 Sep 2021 00:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=DzhfRJtsewrJy9gvg3PVALM7qiexBjbh/6ESbF9yAmQ=; b=i1MTcAD9UnYWPlpu2z9dz7O9pjlQi/vuAb8G6J7B83k+RiE8sojZ6LvZ09CgoUK9n4 LczbRL08HgiCe6YvEYzMEkXDh1Q0J6Jk4GWLqVgxj1Zsl2mmDINOHcH8tljgjekYyuja wbCP62A2N6pG33G7GTvW5WMKXBJcNSykuLc68szTgl3hBj0vHo3E9/Zrank8lIIdBfjG oq7az9SaGonnHEdklABpvcpHh9cJebxCySh26hjrimvfq6LvmneliPGe0KzLyvCsp6eT j/JPRVOpE7YO6zUAsiaElas3DlU350eVSGokG8rpu5d8vz5qH8YDH2eKKlIpOecW7U60 H3/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=DzhfRJtsewrJy9gvg3PVALM7qiexBjbh/6ESbF9yAmQ=; b=UaFj+DX7cbkzfu3IVa6RUpB2tvWMzJTrkTAmI+nZ8Wg6zPISx/+jDXpZf6gHfEZhEy +Fdl/TtptrfqdAHQ+q8dtog9n22yzOLutBpADpWwU1ZuaVmlAzRvUcjbrCwVl63892AX B4VpZ6aBTVvkkpDDRy87U5zAIw3dn83A23PUvSCteT3Fvx/VvwPdjqkt008VD/XKJxsI pEVXhqB02VmHC5eKcoVEmuVN1RrI2y+iemTWdFVGG/UT74ju36SRvzXVSs6mpsU+Un4U IZxHHugNSK6xMlldo7xJS99Nn/nTHRNe5lQrokhyMz/4Pa2yPqTcRtyp+eDVeucmAIZl s5Ew== X-Gm-Message-State: AOAM531zpCIcGDoGMcljRfa5sNikGEf2Ca3sOomKnEFz8v+evbEOn+41 ZaW3deQSf12M64HhZI1nk73pupKF715JcxQqHjs= X-Google-Smtp-Source: ABdhPJwi5zes5aLNI68EPqG8s32AnHOL7SpWjSiidkZRKZ44MpDEG9d4/Z3v+a0xOXreS8EF7zbs/z9Lh4RJ9M+id+w= X-Received: by 2002:ab0:31c1:: with SMTP id e1mr7426551uan.132.1631950623485; Sat, 18 Sep 2021 00:37:03 -0700 (PDT) MIME-Version: 1.0 References: <20210917035736.3934017-1-chenhuacai@loongson.cn> <20210917035736.3934017-19-chenhuacai@loongson.cn> In-Reply-To: From: Huacai Chen Date: Sat, 18 Sep 2021 15:36:52 +0800 Message-ID: Subject: Re: [PATCH V3 18/22] LoongArch: Add PCI controller support To: Arnd Bergmann Cc: Huacai Chen , Andy Lutomirski , Thomas Gleixner , Peter Zijlstra , Andrew Morton , David Airlie , Jonathan Corbet , Linus Torvalds , linux-arch , "open list:DOCUMENTATION" , Linux Kernel Mailing List , Xuefeng Li , Yanteng Si , Jiaxun Yang , Jianmin Lv , ACPI Devel Maling List , "Rafael J. Wysocki" , Len Brown , linux-pci , Will Deacon , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org Hi, Arnd, On Fri, Sep 17, 2021 at 5:02 PM Arnd Bergmann wrote: > > On Fri, Sep 17, 2021 at 5:57 AM Huacai Chen wrote: > > > > Loongson64 based systems are PC-like systems which use PCI/PCIe as its > > I/O bus, This patch adds the PCI host controller support for LoongArch. > > > > Signed-off-by: Jianmin Lv > > Signed-off-by: Huacai Chen > > As discussed before, I think the PCI support should not be part of the > architecture code or this patch series. The headers are ok, but the pci.c > and acpi.c files have nothing loongarch specific in them, and you clearly > just copied most of this from arm64 or x86. In V2 part of the PCI code (pci-loongson.c) has moved to drivers/pci/controllers. For pci.c and acpi.c, I agree that "the thing should be like that", but have some different ideas about "the way to arrive at that". In my opinion, we can let this series be merged at first, and then do another series to "restructure the files and move common parts to the drivers directory". That way looks more natural to me (doing the other series at first may block the whole thing). > > What I would suggest you do instead is: > > - start a separate patch series, addressed to the ACPI, PCI host driver > and ARM64 maintainers. > > - Move all the bits you need from arch/{arm64,ia64,x86} into > drivers/acpi/pci/pci_root.c, duplicating them with #if/#elif/#else > where they are too different, making the #else path the > default that can be shared with loongarch. > > - Move the bits from pci_root_info/acpi_pci_root_info that are > always needed into struct pci_host_bridge, with an > #ifdef CONFIG_ACPI where appropriate. > > - Simplify as much as you can easily do. > > Arnd