From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Tony Luck <tony.luck@intel.com>,
James Morse <james.morse@arm.com>,
Robert Richter <rrichter@marvell.com>,
linux-edac@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Stephen Boyd <swboyd@chromium.org>,
Evan Green <evgreen@chromium.org>,
tsoni@codeaurora.org, psodagud@codeaurora.org,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Subject: [PATCH 1/2] dt-bindings: edac: Add DT bindings for Kryo EDAC
Date: Thu, 5 Dec 2019 09:53:05 +0000 [thread overview]
Message-ID: <0101016ed57a3259-eee09e9e-e99a-40f1-ab1c-63e58a42615c-000000@us-west-2.amazonses.com> (raw)
In-Reply-To: <cover.1575529553.git.saiprakash.ranjan@codeaurora.org>
This adds DT bindings for Kryo EDAC implemented with RAS
extensions on KRYO{3,4}XX CPU cores for reporting of cache
errors.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
.../bindings/edac/qcom-kryo-edac.yaml | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml
diff --git a/Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml b/Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml
new file mode 100644
index 000000000000..1a39429a73b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/qcom-kryo-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kryo Error Detection and Correction(EDAC)
+
+maintainers:
+ - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
+
+description: |
+ Kryo EDAC is defined to describe on-chip error detection and correction
+ for the Kryo CPU cores which implement RAS extensions. It will report
+ all Single Bit Errors and Double Bit Errors found in L1/L2 caches in
+ in two registers ERXSTATUS_EL1 and ERXMISC0_EL1. L3-SCU cache errors
+ are reported in ERR1STATUS and ERR1MISC0 registers.
+ ERXSTATUS_EL1 - Selected Error Record Primary Status Register, EL1
+ ERXMISC0_EL1 - Selected Error Record Miscellaneous Register 0, EL1
+ ERR1STATUS - Error Record Primary Status Register
+ ERR1MISC0 - Error Record Miscellaneous Register 0
+ Current implementation of Kryo ECC(Error Correcting Code) mechanism is
+ based on interrupts.
+
+properties:
+ compatible:
+ enum:
+ - qcom,kryo-edac
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+ items:
+ - description: l1-l2 cache faultirq interrupt
+ - description: l1-l2 cache errirq interrupt
+ - description: l3-scu cache errirq interrupt
+ - description: l3-scu cache faultirq interrupt
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ - const: l1-l2-faultirq
+ - const: l1-l2-errirq
+ - const: l3-scu-errirq
+ - const: l3-scu-faultirq
+
+required:
+ - compatible
+ - interrupts
+ - interrupt-names
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ kryo_edac {
+ compatible = "qcom,kryo-edac";
+ interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "l1-l2-faultirq",
+ "l1-l2-errirq",
+ "l3-scu-errirq",
+ "l3-scu-faultirq";
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next parent reply other threads:[~2019-12-05 9:53 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1575529553.git.saiprakash.ranjan@codeaurora.org>
2019-12-05 9:53 ` Sai Prakash Ranjan [this message]
2019-12-18 23:37 ` [PATCH 1/2] dt-bindings: edac: Add DT bindings for Kryo EDAC Rob Herring
2019-12-19 6:50 ` Sai Prakash Ranjan
2019-12-19 13:58 ` Rob Herring
2019-12-19 14:48 ` Sai Prakash Ranjan
2020-01-15 18:48 ` James Morse
2020-01-24 14:21 ` Sai Prakash Ranjan
2020-02-26 17:12 ` James Morse
2019-12-05 9:53 ` [PATCH 2/2] drivers: edac: Add EDAC support for Kryo CPU caches Sai Prakash Ranjan
[not found] ` <0101016ed57a6311-e815485c-4b77-4342-a3de-203673941602-000000@us-west-2.amazonses.com>
2019-12-11 19:32 ` Evan Green
[not found] ` <5df16ebe.1c69fb81.6481f.a011@mx.google.com>
2019-12-13 5:31 ` Sai Prakash Ranjan
[not found] ` <0101016ed57a6559-46c6c649-db28-4945-a11c-7441b8e9ac5b-000000@us-west-2.amazonses.com>
2019-12-30 11:50 ` Borislav Petkov
2020-01-13 5:44 ` Sai Prakash Ranjan
2020-01-15 18:49 ` James Morse
2020-01-24 14:52 ` Sai Prakash Ranjan
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