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From: James Morse <>
To: Sai Prakash Ranjan <>
Cc: Andy Gross <>,
	Bjorn Andersson <>,
	Mark Rutland <>,
	Rob Herring <>,, Borislav Petkov <>,
	Mauro Carvalho Chehab <>,
	Tony Luck <>,
	Robert Richter <>,,,,,
	Evan Green <>,
	Stephen Boyd <>,,,
Subject: Re: [PATCH 0/2] Add EDAC support for Kryo CPU core caches
Date: Wed, 15 Jan 2020 18:46:07 +0000
Message-ID: <> (raw)
In-Reply-To: <>

Hi Sai,

(CC: +Tyler)

On 05/12/2019 09:52, Sai Prakash Ranjan wrote:
> This series implements EDAC support for error reporting on
> Kryo{3,4}XX CPU caches L1,L2, L3-SCU. All the cores(big.LITTLE)
> in Kryo{3,4}XX CPUs implement RAS extensions and use interrupt
> based ECC mechanism to report errors.
> This series has been tested on SC7180, SDM845, SM8150 SoCs with
> Kryo{3,4}XX CPU cores based on ARM Cortex-A55, Cortex-A75 and
> Cortex-A76.
> This implementation is platform specific in contrast to the
> patch posted last time for generic error reporting on arm cortex
> implementations with RAS extensions by Kyle Yan.
>  -

I think that series was dropped because it was too soc-specific and overlaps with the v8.2
kernel first support. That series was superseded by:

Can you work with Tyler on a combined series? The combined support may need to look quite
different. (DT and big/little being the obvious differences).

I'm afraid this is the tip of the kernel-first-RAS iceberg.



       reply index

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <>
2020-01-15 18:46 ` James Morse [this message]
2020-01-24 14:04   ` Sai Prakash Ranjan
2019-12-05  9:52 Sai Prakash Ranjan

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