From: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
To: <tony.luck@intel.com>, <bp@alien8.de>, <tglx@linutronix.de>,
<mingo@redhat.com>, <hpa@zytor.com>, <x86@kernel.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<yazen.ghannam@amd.com>, <vishal.l.verma@intel.com>,
<qiuxu.zhuo@intel.com>
Cc: <DavidWang@zhaoxin.com>, <CooperYan@zhaoxin.com>,
<QiyuanWang@zhaoxin.com>, <HerryYang@zhaoxin.com>
Subject: [PATCH v4 4/4] x86/mce: Add Zhaoxin LMCE support
Date: Wed, 18 Sep 2019 14:19:33 +0800 [thread overview]
Message-ID: <1568787573-1297-5-git-send-email-TonyWWang-oc@zhaoxin.com> (raw)
In-Reply-To: <1568787573-1297-4-git-send-email-TonyWWang-oc@zhaoxin.com>
Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
---
arch/x86/kernel/cpu/mce/core.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 65c5a1f..88a9622 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1132,6 +1132,12 @@ static bool __mc_check_crashing_cpu(int cpu)
u64 mcgstatus;
mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
+ if (mcgstatus & MCG_STATUS_LMCES)
+ return false;
+ }
+
if (mcgstatus & MCG_STATUS_RIPV) {
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
return true;
@@ -1282,9 +1288,10 @@ void do_machine_check(struct pt_regs *regs, long error_code)
/*
* Check if this MCE is signaled to only this logical processor,
- * on Intel only.
+ * on Intel, Zhaoxin only.
*/
- if (m.cpuvendor == X86_VENDOR_INTEL)
+ if (m.cpuvendor == X86_VENDOR_INTEL ||
+ m.cpuvendor == X86_VENDOR_ZHAOXIN)
lmce = m.mcgstatus & MCG_STATUS_LMCES;
/*
@@ -1795,9 +1802,15 @@ static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
}
intel_init_cmci();
+ intel_init_lmce();
mce_adjust_timer = cmci_intel_adjust_timer;
}
+static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1834,6 +1847,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
case X86_VENDOR_INTEL:
mce_intel_feature_clear(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_clear(c);
+ break;
default:
break;
}
--
2.7.4
next prev parent reply other threads:[~2019-09-18 6:19 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-18 6:19 [PATCH v4 0/4] x86/mce: Add supports for Zhaoxin MCA Tony W Wang-oc
2019-09-18 6:19 ` [PATCH v4 1/4] x86/mce: Add Zhaoxin MCE support Tony W Wang-oc
2019-09-18 6:19 ` [PATCH v4 2/4] x86/mce: Make 3 functions non-static Tony W Wang-oc
2019-09-18 6:19 ` [PATCH v4 3/4] x86/mce: Add Zhaoxin CMCI support Tony W Wang-oc
2019-09-18 6:19 ` Tony W Wang-oc [this message]
2019-10-01 11:21 ` [tip: ras/core] x86/mce: Add Zhaoxin LMCE support tip-bot2 for Tony W Wang-oc
2019-10-01 11:21 ` [tip: ras/core] x86/mce: Add Zhaoxin CMCI support tip-bot2 for Tony W Wang-oc
2019-09-30 16:25 ` [PATCH v4 2/4] x86/mce: Make 3 functions non-static Borislav Petkov
2019-10-01 11:21 ` [tip: ras/core] x86/mce: Add Zhaoxin MCE support tip-bot2 for Tony W Wang-oc
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