From: sherry sun <sherry.sun@nxp.com>
To: bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com,
james.morse@arm.com, rrichter@marvell.com,
michal.simek@xilinx.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, robh+dt@kernel.org, mark.rutland@arm.com
Cc: linux-edac@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-imx@nxp.com, frank.li@nxp.com
Subject: [PATCH 1/3] dt-bindings: memory-controllers: Add i.MX8MP DDRC binding doc
Date: Fri, 21 Feb 2020 14:39:14 +0800 [thread overview]
Message-ID: <1582267156-20189-2-git-send-email-sherry.sun@nxp.com> (raw)
In-Reply-To: <1582267156-20189-1-git-send-email-sherry.sun@nxp.com>
From: Sherry Sun <sherry.sun@nxp.com>
Add documentation for i.MX8MP DDRC binding based on synopsys_edac doc,
which use the same memory-controller IP.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
.../devicetree/bindings/memory-controllers/synopsys.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
index 9d32762c47e1..5c03959a451f 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
@@ -6,16 +6,20 @@ bus width configurations.
The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration.
-These both ECC controllers correct single bit ECC errors and detect double bit
+The i.MX8MP DDR ECC controller has an ECC support in 64-bit bus width
+configurations.
+
+These all ECC controllers correct single bit ECC errors and detect double bit
ECC errors.
Required properties:
- compatible: One of:
- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
+ - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller
- reg: Should contain DDR controller registers location and length.
-Required properties for "xlnx,zynqmp-ddrc-2.40a":
+Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc":
- interrupts: Property with a value describing the interrupt number.
Example:
--
2.17.1
next prev parent reply other threads:[~2020-02-21 6:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-21 6:39 [PATCH 0/3] Add edac driver for i.MX8MP based on synopsys edac driver sherry sun
2020-02-21 6:39 ` sherry sun [this message]
2020-02-26 17:24 ` [PATCH 1/3] dt-bindings: memory-controllers: Add i.MX8MP DDRC binding doc Rob Herring
2020-02-27 6:40 ` Sherry Sun
2020-02-21 6:39 ` [PATCH 2/3] EDAC: Add synopsys edac driver support for i.MX8MP sherry sun
2020-02-21 6:39 ` [PATCH 3/3] EDAC: synopsys: Add " sherry sun
2020-02-26 17:12 ` James Morse
2020-02-27 5:00 ` Sherry Sun
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