From: Chris Packham <chris.packham@alliedtelesis.co.nz>
To: linux@armlinux.org.uk, bp@alien8.de, mark.rutland@arm.com,
robh+dt@kernel.org, mchehab@kernel.org, james.morse@arm.com,
jlu@pengutronix.de, gregory.clement@bootlin.com
Cc: linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Gregory CLEMENT <gregory.clement@free-electrons.com>,
Chris Packham <chris.packham@alliedtelesis.co.nz>
Subject: [PATCH v8 2/9] ARM: aurora-l2: add prefix to MAX_RANGE_SIZE
Date: Fri, 10 May 2019 22:15:29 +1200 [thread overview]
Message-ID: <20190510101536.6724-3-chris.packham@alliedtelesis.co.nz> (raw)
In-Reply-To: <20190510101536.6724-1-chris.packham@alliedtelesis.co.nz>
From: Jan Luebbe <jlu@pengutronix.de>
The macro name is too generic, so add a AURORA_ prefix.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
arch/arm/mm/cache-l2x0.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h
index c86124769831..dc5c479ec4c3 100644
--- a/arch/arm/include/asm/hardware/cache-aurora-l2.h
+++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
@@ -41,7 +41,7 @@
#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \
(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
-#define MAX_RANGE_SIZE 1024
+#define AURORA_MAX_RANGE_SIZE 1024
#define AURORA_WAY_SIZE_SHIFT 2
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a00d6f7fd34c..7d2d2a3c67d0 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1364,8 +1364,8 @@ static unsigned long aurora_range_end(unsigned long start, unsigned long end)
* since cache range operations stall the CPU pipeline
* until completion.
*/
- if (end > start + MAX_RANGE_SIZE)
- end = start + MAX_RANGE_SIZE;
+ if (end > start + AURORA_MAX_RANGE_SIZE)
+ end = start + AURORA_MAX_RANGE_SIZE;
/*
* Cache range operations can't straddle a page boundary.
--
2.21.0
next prev parent reply other threads:[~2019-05-10 10:16 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-10 10:15 [PATCH v8 0/9] EDAC drivers for Armada XP L2 and DDR Chris Packham
2019-05-10 10:15 ` [PATCH v8 1/9] ARM: l2c: move cache-aurora-l2.h to asm/hardware Chris Packham
2019-05-10 10:15 ` Chris Packham [this message]
2019-05-10 10:15 ` [PATCH v8 3/9] ARM: aurora-l2: add defines for parity and ECC registers Chris Packham
2019-05-10 10:15 ` [PATCH v8 4/9] ARM: l2x0: support parity-enable/disable on aurora Chris Packham
2019-05-10 10:15 ` [PATCH v8 5/9] dt-bindings: ARM: document marvell,ecc-enable binding Chris Packham
2019-05-10 10:15 ` [PATCH v8 6/9] ARM: l2x0: add marvell,ecc-enable property for aurora Chris Packham
2019-05-10 10:15 ` [PATCH v8 7/9] EDAC: Add missing debugfs_create_x32 wrapper Chris Packham
2019-05-10 10:15 ` [PATCH v8 8/9] EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC Chris Packham
2019-05-10 10:15 ` [PATCH v8 9/9] EDAC: armada_xp: Add support for more SoCs Chris Packham
2019-06-07 0:47 ` [PATCH v8 0/9] EDAC drivers for Armada XP L2 and DDR Chris Packham
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