From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91614C04AB2 for ; Fri, 10 May 2019 10:16:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5FEFA2175B for ; Fri, 10 May 2019 10:16:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="ly8BsxX3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727376AbfEJKQv (ORCPT ); Fri, 10 May 2019 06:16:51 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:47624 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727302AbfEJKPn (ORCPT ); Fri, 10 May 2019 06:15:43 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id A38E2891AC; Fri, 10 May 2019 22:15:40 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1557483340; bh=rC/ldNBQ62uARFK7cDeSAl/BYe+4iwU1kkx4L4JMo3U=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ly8BsxX38zvGDEoQoIgcRh3LZBoKZdk7xd6v6vOL6r5vqMUoglrP9bWx4nMpt/2DK l29DLSNMzVQBQf1BFuK/BtsL1mx7Wr4IPJC4299aRdKx4nvp94iQHlQ34FPFuLClwx NpHXaGJFM0QFCmXIONxzK+hlWR5d232+swdHbDlAByhcpvvO+CzeXQDEKXgMZIoAkn HdFKOEgsljYSyKN1ilr2NG4vH1mNCt3kkbkI2KGlbzyCr7fdfROHtGQi3ChFpo1F3a gpUdm6Mie1cmqMvQxkhpyvU/jt5umsIhDZtYxym9+HgfI6AKAkvBSIU2BXV7mJ/j7s ahb66yw3rUk7Q== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Fri, 10 May 2019 22:15:41 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 49F3413EF9E; Fri, 10 May 2019 22:15:40 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id D2F681E1D5B; Fri, 10 May 2019 22:15:39 +1200 (NZST) From: Chris Packham To: linux@armlinux.org.uk, bp@alien8.de, mark.rutland@arm.com, robh+dt@kernel.org, mchehab@kernel.org, james.morse@arm.com, jlu@pengutronix.de, gregory.clement@bootlin.com Cc: linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v8 6/9] ARM: l2x0: add marvell,ecc-enable property for aurora Date: Fri, 10 May 2019 22:15:33 +1200 Message-Id: <20190510101536.6724-7-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190510101536.6724-1-chris.packham@alliedtelesis.co.nz> References: <20190510101536.6724-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable x-atlnz-ls: pat Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The aurora cache on the Marvell Armada-XP SoC supports ECC protection for the L2 data arrays. Add a "marvell,ecc-enable" device tree property which can be used to enable this. Signed-off-by: Chris Packham [jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN] Signed-off-by: Jan Luebbe --- Notes: Changes in v7: - remove marvell,ecc-disable arch/arm/mm/cache-l2x0.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index b70bee74750d..e5380f7b14a5 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1505,6 +1505,11 @@ static void __init aurora_of_parse(const struct de= vice_node *np, mask |=3D AURORA_ACR_FORCE_WRITE_POLICY_MASK; } =20 + if (of_property_read_bool(np, "marvell,ecc-enable")) { + mask |=3D AURORA_ACR_ECC_EN; + val |=3D AURORA_ACR_ECC_EN; + } + if (of_property_read_bool(np, "arm,parity-enable")) { mask |=3D AURORA_ACR_PARITY_EN; val |=3D AURORA_ACR_PARITY_EN; --=20 2.21.0