From: "Luck, Tony" <tony.luck@intel.com>
To: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bp@suse.de" <bp@suse.de>, "x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH v3 5/6] x86/MCE: Save MCA control bits that get set in hardware
Date: Thu, 16 May 2019 08:52:02 -0700 [thread overview]
Message-ID: <20190516155202.GA11517@agluck-desk> (raw)
In-Reply-To: <20190430203206.104163-6-Yazen.Ghannam@amd.com>
On Tue, Apr 30, 2019 at 08:32:20PM +0000, Ghannam, Yazen wrote:
> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
> index 986de830f26e..551366c155ef 100644
> --- a/arch/x86/kernel/cpu/mce/core.c
> +++ b/arch/x86/kernel/cpu/mce/core.c
> @@ -1567,10 +1567,13 @@ static void __mcheck_cpu_init_clear_banks(void)
> for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
> struct mce_bank *b = &mce_banks[i];
>
> - if (!b->init)
> - continue;
> - wrmsrl(msr_ops.ctl(i), b->ctl);
> - wrmsrl(msr_ops.status(i), 0);
> + if (b->init) {
> + wrmsrl(msr_ops.ctl(i), b->ctl);
> + wrmsrl(msr_ops.status(i), 0);
> + }
> +
> + /* Save bits set in hardware. */
> + rdmsrl(msr_ops.ctl(i), b->ctl);
> }
> }
This looks like it will be a problem for Intel CPUs. If
we take a CPU offline, and then bring it back again, we
ues "b->ctl" to reinitialize the register in mce_reenable_cpu().
But Intel SDM says at the end of section "15.3.2.1 IA32_MCi_CTL_MSRs"
"P6 family processors only allow the writing of all 1s or all
0s to the IA32_MCi_CTL MSR."
-Tony
next prev parent reply other threads:[~2019-05-16 15:52 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-30 20:32 [PATCH v3 0/6] Handle MCA banks in a per_cpu way Ghannam, Yazen
2019-04-30 20:32 ` [v3,1/6] x86/MCE: Make struct mce_banks[] static Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 1/6] " Ghannam, Yazen
2019-04-30 20:32 ` [v3,2/6] x86/MCE: Handle MCA controls in a per_cpu way Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 2/6] " Ghannam, Yazen
2019-04-30 20:32 ` [v3,3/6] x86/MCE/AMD: Don't cache block addresses on SMCA systems Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 3/6] " Ghannam, Yazen
2019-04-30 20:32 ` [v3,5/6] x86/MCE: Save MCA control bits that get set in hardware Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 5/6] " Ghannam, Yazen
2019-05-16 15:52 ` Luck, Tony [this message]
2019-05-16 16:14 ` Ghannam, Yazen
2019-05-16 16:56 ` Borislav Petkov
2019-05-16 17:09 ` Ghannam, Yazen
2019-05-16 17:21 ` Borislav Petkov
2019-05-16 20:20 ` Ghannam, Yazen
2019-05-16 20:34 ` Borislav Petkov
2019-05-16 20:59 ` Luck, Tony
2019-05-17 10:10 ` Borislav Petkov
2019-05-17 15:46 ` Ghannam, Yazen
2019-05-17 16:37 ` Borislav Petkov
2019-05-17 17:26 ` Luck, Tony
2019-05-17 17:48 ` Borislav Petkov
2019-05-17 18:06 ` Luck, Tony
2019-05-17 19:34 ` Borislav Petkov
2019-05-17 19:44 ` Luck, Tony
2019-05-17 19:50 ` Borislav Petkov
2019-05-17 19:49 ` Ghannam, Yazen
2019-05-17 20:02 ` Borislav Petkov
2019-05-23 20:00 ` Ghannam, Yazen
2019-05-27 23:28 ` Borislav Petkov
2019-06-07 14:49 ` Ghannam, Yazen
2019-06-07 16:37 ` Borislav Petkov
2019-06-07 16:44 ` Ghannam, Yazen
2019-06-07 16:59 ` Borislav Petkov
2019-06-07 17:08 ` Ghannam, Yazen
2019-06-07 17:20 ` Borislav Petkov
2019-06-11 5:13 ` Borislav Petkov
2019-04-30 20:32 ` [v3,4/6] x86/MCE: Make number of MCA banks per_cpu Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 4/6] " Ghannam, Yazen
2019-05-18 11:25 ` Borislav Petkov
2019-05-21 17:52 ` Ghannam, Yazen
2019-05-21 20:29 ` Borislav Petkov
2019-05-21 20:42 ` Luck, Tony
2019-05-21 23:09 ` Borislav Petkov
2019-05-22 14:01 ` Ghannam, Yazen
2019-04-30 20:32 ` [v3,6/6] x86/MCE: Treat MCE bank as initialized if control bits set in hardware Yazen Ghannam
2019-04-30 20:32 ` [PATCH v3 6/6] " Ghannam, Yazen
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