* [PATCH v2] EDAC support for SiFive SoCs @ 2019-05-06 11:27 Yash Shah 2019-05-06 11:27 ` [PATCH v2] edac: sifive: Add EDAC platform driver " Yash Shah 0 siblings, 1 reply; 7+ messages in thread From: Yash Shah @ 2019-05-06 11:27 UTC (permalink / raw) To: linux-edac, linux-riscv, palmer, bp, james.morse Cc: paul.walmsley, linux-kernel, aou, mchehab, sachin.ghadi, davem, gregkh, nicolas.ferre, paulmck, Yash Shah Adds an EDAC platform driver for SiFive SoCs. This patch was earlier part of the patch series: 'L2 cache controller and EDAC support for SiFive SoCs' https://lkml.org/lkml/2019/4/15/320 In order to merge L2 cache controller driver without any dependency on EDAC, this EDAC patch is re-posted separately with updated MAINTAINERS entry. This patch depends on patch 'RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs' https://lkml.org/lkml/2019/5/6/255 The EDAC driver registers for notifier events from the L2 cache controller driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events The patch is based on Linux 5.1-rc2 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/L2_cache_controller branch of: https://github.com/yashshah7/riscv-linux.git Changes since v1 - Move extern definition into sifive_l2_cache header file - Replace NOTIFY_STOP with NOTIFY_OK in ecc_err_event() - Other minor fixes based upon comments against v1 Yash Shah (1): edac: sifive: Add EDAC platform driver for SiFive SoCs MAINTAINERS | 6 +++ arch/riscv/Kconfig | 1 + drivers/edac/Kconfig | 6 +++ drivers/edac/Makefile | 1 + drivers/edac/sifive_edac.c | 119 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 133 insertions(+) create mode 100644 drivers/edac/sifive_edac.c -- 1.9.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs 2019-05-06 11:27 [PATCH v2] EDAC support for SiFive SoCs Yash Shah @ 2019-05-06 11:27 ` Yash Shah 2019-05-21 5:30 ` Yash Shah 0 siblings, 1 reply; 7+ messages in thread From: Yash Shah @ 2019-05-06 11:27 UTC (permalink / raw) To: linux-edac, linux-riscv, palmer, bp, james.morse Cc: paul.walmsley, linux-kernel, aou, mchehab, sachin.ghadi, davem, gregkh, nicolas.ferre, paulmck, Yash Shah The initial ver of EDAC driver supports: - ECC event monitoring and reporting through the EDAC framework for SiFive L2 cache controller. The EDAC driver registers for notifier events from the L2 cache controller driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: James Morse <james.morse@arm.com> --- This patch depends on patch 'RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs' https://lkml.org/lkml/2019/5/6/255 MAINTAINERS | 6 +++ arch/riscv/Kconfig | 1 + drivers/edac/Kconfig | 6 +++ drivers/edac/Makefile | 1 + drivers/edac/sifive_edac.c | 119 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 133 insertions(+) create mode 100644 drivers/edac/sifive_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index ba4f104..50f9f43 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5679,6 +5679,12 @@ L: linux-edac@vger.kernel.org S: Maintained F: drivers/edac/sb_edac.c +EDAC-SIFIVE +M: Yash Shah <yash.shah@sifive.com> +L: linux-edac@vger.kernel.org +S: Supported +F: drivers/edac/sifive_edac.c + EDAC-SKYLAKE M: Tony Luck <tony.luck@intel.com> L: linux-edac@vger.kernel.org diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index eb56c82..31999a6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -49,6 +49,7 @@ config RISCV select GENERIC_IRQ_MULTI_HANDLER select ARCH_HAS_PTE_SPECIAL select HAVE_EBPF_JIT if 64BIT + select EDAC_SUPPORT config MMU def_bool y diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 47eb4d1..3e05228 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,6 +460,12 @@ config EDAC_ALTERA_SDMMC Support for error detection and correction on the Altera SDMMC FIFO Memory for Altera SoCs. +config EDAC_SIFIVE + bool "Sifive platform EDAC driver" + depends on EDAC=y && RISCV + help + Support for error detection and correction on the SiFive SoCs. + config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" depends on ARCH_ZYNQ || ARCH_ZYNQMP diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 89ad4a84..165ca65e 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o obj-$(CONFIG_EDAC_THUNDERX) += thunderx_edac.o obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o +obj-$(CONFIG_EDAC_SIFIVE) += sifive_edac.o obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c new file mode 100644 index 0000000..413cdb4 --- /dev/null +++ b/drivers/edac/sifive_edac.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SiFive Platform EDAC Driver + * + * Copyright (C) 2018-2019 SiFive, Inc. + * + * This driver is partially based on octeon_edac-pc.c + * + */ +#include <linux/edac.h> +#include <linux/platform_device.h> +#include "edac_module.h" +#include <asm/sifive_l2_cache.h> + +#define DRVNAME "sifive_edac" + +struct sifive_edac_priv { + struct notifier_block notifier; + struct edac_device_ctl_info *dci; +}; + +/** + * EDAC error callback + * + * @event: non-zero if unrecoverable. + */ +static +int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + const char *msg = (char *)ptr; + struct sifive_edac_priv *p; + + p = container_of(this, struct sifive_edac_priv, notifier); + + if (event == SIFIVE_L2_ERR_TYPE_UE) + edac_device_handle_ue(p->dci, 0, 0, msg); + else if (event == SIFIVE_L2_ERR_TYPE_CE) + edac_device_handle_ce(p->dci, 0, 0, msg); + + return NOTIFY_OK; +} + +static int ecc_register(struct platform_device *pdev) +{ + struct sifive_edac_priv *p; + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + p->notifier.notifier_call = ecc_err_event; + platform_set_drvdata(pdev, p); + + p->dci = edac_device_alloc_ctl_info(0, "sifive_ecc", 1, "sifive_ecc", + 1, 1, NULL, 0, + edac_device_alloc_index()); + if (IS_ERR(p->dci)) + return PTR_ERR(p->dci); + + p->dci->dev = &pdev->dev; + p->dci->mod_name = "Sifive ECC Manager"; + p->dci->ctl_name = dev_name(&pdev->dev); + p->dci->dev_name = dev_name(&pdev->dev); + + if (edac_device_add_device(p->dci)) { + dev_err(p->dci->dev, "failed to register with EDAC core\n"); + goto err; + } + + register_sifive_l2_error_notifier(&p->notifier); + + return 0; + +err: + edac_device_free_ctl_info(p->dci); + + return -ENXIO; +} + +static int ecc_unregister(struct platform_device *pdev) +{ + struct sifive_edac_priv *p = platform_get_drvdata(pdev); + + unregister_sifive_l2_error_notifier(&p->notifier); + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(p->dci); + + return 0; +} + +static struct platform_device *sifive_pdev; + +static int __init sifive_edac_init(void) +{ + int ret; + + sifive_pdev = platform_device_register_simple(DRVNAME, 0, NULL, 0); + if (IS_ERR(sifive_pdev)) + return PTR_ERR(sifive_pdev); + + ret = ecc_register(sifive_pdev); + if (ret) + platform_device_unregister(sifive_pdev); + + return ret; +} + +static void __exit sifive_edac_exit(void) +{ + ecc_unregister(sifive_pdev); + platform_device_unregister(sifive_pdev); +} + +module_init(sifive_edac_init); +module_exit(sifive_edac_exit); + +MODULE_AUTHOR("SiFive Inc."); +MODULE_DESCRIPTION("SiFive platform EDAC driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs 2019-05-06 11:27 ` [PATCH v2] edac: sifive: Add EDAC platform driver " Yash Shah @ 2019-05-21 5:30 ` Yash Shah 2019-05-21 18:21 ` Borislav Petkov 0 siblings, 1 reply; 7+ messages in thread From: Yash Shah @ 2019-05-21 5:30 UTC (permalink / raw) To: linux-edac, linux-riscv, Palmer Dabbelt, Borislav Petkov, James Morse Cc: Paul Walmsley, linux-kernel, aou, mchehab, Sachin Ghadi, davem, gregkh, nicolas.ferre, paulmck On Mon, May 6, 2019 at 4:57 PM Yash Shah <yash.shah@sifive.com> wrote: > > The initial ver of EDAC driver supports: > - ECC event monitoring and reporting through the EDAC framework for SiFive > L2 cache controller. > > The EDAC driver registers for notifier events from the L2 cache controller > driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > Reviewed-by: James Morse <james.morse@arm.com> > --- > This patch depends on patch > 'RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs' > https://lkml.org/lkml/2019/5/6/255 The prerequisite patch (sifive_l2_cache driver) has been merged into mainline v5.2-rc1 It should be OK to merge this edac driver now. - Yash ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs 2019-05-21 5:30 ` Yash Shah @ 2019-05-21 18:21 ` Borislav Petkov 2019-05-22 9:13 ` James Morse 0 siblings, 1 reply; 7+ messages in thread From: Borislav Petkov @ 2019-05-21 18:21 UTC (permalink / raw) To: Yash Shah, James Morse Cc: linux-edac, linux-riscv, Palmer Dabbelt, James Morse, Paul Walmsley, linux-kernel, aou, mchehab, Sachin Ghadi, davem, gregkh, nicolas.ferre, paulmck On Tue, May 21, 2019 at 11:00:59AM +0530, Yash Shah wrote: > The prerequisite patch (sifive_l2_cache driver) has been merged into > mainline v5.2-rc1 > It should be OK to merge this edac driver now. James? -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. Srsly. ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs 2019-05-21 18:21 ` Borislav Petkov @ 2019-05-22 9:13 ` James Morse 2019-05-22 9:34 ` Boris Petkov 0 siblings, 1 reply; 7+ messages in thread From: James Morse @ 2019-05-22 9:13 UTC (permalink / raw) To: Borislav Petkov Cc: Yash Shah, linux-edac, linux-riscv, Palmer Dabbelt, Paul Walmsley, linux-kernel, aou, mchehab, Sachin Ghadi, davem, gregkh, nicolas.ferre, paulmck Hi Boris, On 21/05/2019 19:21, Borislav Petkov wrote: > On Tue, May 21, 2019 at 11:00:59AM +0530, Yash Shah wrote: >> The prerequisite patch (sifive_l2_cache driver) has been merged into >> mainline v5.2-rc1 >> It should be OK to merge this edac driver now. > > James? Still fine by me: Reviewed-by: James Morse <james.morse@arm.com> (...this patch already has my reviewed-by on it...) I commented that it couldn't be merged in pieces here: https://lore.kernel.org/lkml/4072c812-d3bf-9ad5-2b30-6b2a5060bb55@arm.com/T/#u which is what Yash is replying to. Thanks, James ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs 2019-05-22 9:13 ` James Morse @ 2019-05-22 9:34 ` Boris Petkov 2019-06-07 6:43 ` Borislav Petkov 0 siblings, 1 reply; 7+ messages in thread From: Boris Petkov @ 2019-05-22 9:34 UTC (permalink / raw) To: James Morse Cc: Yash Shah, linux-edac, linux-riscv, Palmer Dabbelt, Paul Walmsley, linux-kernel, aou, mchehab, Sachin Ghadi, davem, gregkh, nicolas.ferre, paulmck On May 22, 2019 4:13:59 AM CDT, James Morse <james.morse@arm.com> wrote: >Hi Boris, > >On 21/05/2019 19:21, Borislav Petkov wrote: >> On Tue, May 21, 2019 at 11:00:59AM +0530, Yash Shah wrote: >>> The prerequisite patch (sifive_l2_cache driver) has been merged into >>> mainline v5.2-rc1 >>> It should be OK to merge this edac driver now. >> >> James? > >Still fine by me: >Reviewed-by: James Morse <james.morse@arm.com> > >(...this patch already has my reviewed-by on it...) > >I commented that it couldn't be merged in pieces here: >https://lore.kernel.org/lkml/4072c812-d3bf-9ad5-2b30-6b2a5060bb55@arm.com/T/#u > >which is what Yash is replying to. Ok, I'll take it when I get back. Thanks for clarifying. -- Sent from a small device: formatting sux and brevity is inevitable. ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs 2019-05-22 9:34 ` Boris Petkov @ 2019-06-07 6:43 ` Borislav Petkov 0 siblings, 0 replies; 7+ messages in thread From: Borislav Petkov @ 2019-06-07 6:43 UTC (permalink / raw) To: James Morse, Yash Shah Cc: linux-edac, linux-riscv, Palmer Dabbelt, Paul Walmsley, linux-kernel, aou, mchehab, Sachin Ghadi, davem, gregkh, nicolas.ferre, paulmck On Wed, May 22, 2019 at 04:34:38AM -0500, Boris Petkov wrote: > >Still fine by me: > >Reviewed-by: James Morse <james.morse@arm.com> > > > >(...this patch already has my reviewed-by on it...) > > > >I commented that it couldn't be merged in pieces here: > >https://lore.kernel.org/lkml/4072c812-d3bf-9ad5-2b30-6b2a5060bb55@arm.com/T/#u > > > >which is what Yash is replying to. > > Ok, I'll take it when I get back. Thanks for clarifying. Now queued. Thx. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-06-07 6:43 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-05-06 11:27 [PATCH v2] EDAC support for SiFive SoCs Yash Shah 2019-05-06 11:27 ` [PATCH v2] edac: sifive: Add EDAC platform driver " Yash Shah 2019-05-21 5:30 ` Yash Shah 2019-05-21 18:21 ` Borislav Petkov 2019-05-22 9:13 ` James Morse 2019-05-22 9:34 ` Boris Petkov 2019-06-07 6:43 ` Borislav Petkov
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