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From: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bp@suse.de" <bp@suse.de>,
	"tony.luck@intel.com" <tony.luck@intel.com>,
	"x86@kernel.org" <x86@kernel.org>
Subject: [PATCH v4 5/5] x86/MCE: Determine MCA banks' init state properly
Date: Fri, 7 Jun 2019 20:18:06 +0000
Message-ID: <20190607201752.221446-6-Yazen.Ghannam@amd.com> (raw)
In-Reply-To: <20190607201752.221446-1-Yazen.Ghannam@amd.com>

From: Yazen Ghannam <yazen.ghannam@amd.com>

The OS is expected to write all bits to MCA_CTL for each bank,
thus enabling error reporting in all banks. However, some banks
may be unused in which case the registers for such banks are
Read-as-Zero/Writes-Ignored. Also, the OS may avoid setting some control
bits because of quirks, etc.

A bank can be considered uninitialized if the MCA_CTL register returns
zero. This is because either the OS did not write anything or because
the hardware is enforcing RAZ/WI for the bank.

Set a bank's init value based on if the control bits are set or not in
hardware. Return an error code in the sysfs interface for uninitialized
banks.

Do a final bank init check in a separate function which is not part of
any user-controlled code flows. This is so a user may enable/disable a
bank during runtime without having to restart their system.

 [ bp: Massage a bit. Discover bank init state at boot. ]

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190430203206.104163-6-Yazen.Ghannam@amd.com

v3->v4:
* Patch 5 version 3 was zapped.
* This is based on new patch from Boris which was based on Patch 6 version 3.
* Reworked new patch to fix sysfs issue with disabled banks.

v2->v3:
* No change.

v1->v2:
* No change.

 arch/x86/kernel/cpu/mce/core.c | 39 ++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 6813712d8648..ae7723a942f6 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1490,6 +1490,11 @@ static void __mcheck_cpu_mce_banks_init(void)
 	for (i = 0; i < n_banks; i++) {
 		struct mce_bank *b = &mce_banks[i];
 
+		/*
+		 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
+		 * the required vendor quirks before
+		 * __mcheck_cpu_init_clear_banks() does the final bank setup.
+		 */
 		b->ctl = -1ULL;
 		b->init = 1;
 	}
@@ -1562,6 +1567,33 @@ static void __mcheck_cpu_init_clear_banks(void)
 	}
 }
 
+/*
+ * Do a final check to see if there are any unused/RAZ banks.
+ *
+ * This must be done after the banks have been initialized and any quirks have
+ * been applied.
+ *
+ * Do not call this from any user-initialed flows, e.g. CPU hotplug or sysfs.
+ * Otherwise, a user who disables a bank will not be able to re-enable it
+ * without a system reboot.
+ */
+static void __mcheck_cpu_check_banks(void)
+{
+	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+	u64 msrval;
+	int i;
+
+	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
+		struct mce_bank *b = &mce_banks[i];
+
+		if (!b->init)
+			continue;
+
+		rdmsrl(msr_ops.ctl(i), msrval);
+		b->init = !!msrval;
+	}
+}
+
 /*
  * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
  * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
@@ -1849,6 +1881,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
 	__mcheck_cpu_init_generic();
 	__mcheck_cpu_init_vendor(c);
 	__mcheck_cpu_init_clear_banks();
+	__mcheck_cpu_check_banks();
 	__mcheck_cpu_setup_timer();
 }
 
@@ -2085,6 +2118,9 @@ static ssize_t show_bank(struct device *s, struct device_attribute *attr,
 
 	b = &per_cpu(mce_banks_array, s->id)[bank];
 
+	if (!b->init)
+		return -ENODEV;
+
 	return sprintf(buf, "%llx\n", b->ctl);
 }
 
@@ -2103,6 +2139,9 @@ static ssize_t set_bank(struct device *s, struct device_attribute *attr,
 
 	b = &per_cpu(mce_banks_array, s->id)[bank];
 
+	if (!b->init)
+		return -ENODEV;
+
 	b->ctl = new;
 	mce_restart();
 
-- 
2.17.1


  parent reply index

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-07 20:18 [PATCH v4 0/5] Handle MCA banks in a per_cpu way Ghannam, Yazen
2019-06-07 20:18 ` [PATCH v4 1/5] x86/MCE: Make struct mce_banks[] static Ghannam, Yazen
2019-06-11 16:22   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2019-06-07 20:18 ` [PATCH v4 2/5] x86/MCE: Make mce_banks a per-CPU array Ghannam, Yazen
2019-06-11 16:23   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2019-06-07 20:18 ` [PATCH v4 3/5] x86/MCE/AMD: Don't cache block addresses on SMCA systems Ghannam, Yazen
2019-06-11 16:24   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2019-06-07 20:18 ` [PATCH v4 4/5] x86/MCE: Make the number of MCA banks a per-CPU variable Ghannam, Yazen
2019-06-11 16:25   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2019-06-07 20:18 ` Ghannam, Yazen [this message]
2019-06-11 16:25   ` [tip:ras/core] x86/MCE: Determine MCA banks' init state properly tip-bot for Yazen Ghannam

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