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From: Borislav Petkov <bp@alien8.de>
To: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/8] EDAC/amd64: Fix number of DIMMs and Chip Select bases/masks on Family17h
Date: Mon, 17 Jun 2019 15:37:35 +0200
Message-ID: <20190617133735.GJ27127@zn.tnic> (raw)
In-Reply-To: <SN6PR12MB263988EC0AC99DA2D29B21F3F8EF0@SN6PR12MB2639.namprd12.prod.outlook.com>

On Thu, Jun 13, 2019 at 09:00:19PM +0000, Ghannam, Yazen wrote:
> Do you have any tips on how to handle it? I'm thinking it may be
> tricky because of the ranges and multiple variables.

It ain't pretty. It seems the if-else thing is still better, after all.

---
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 873437be86d9..16235c0ef7e5 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -936,13 +936,25 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
  */
 static void prep_chip_selects(struct amd64_pvt *pvt)
 {
-	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
+	switch (pvt->fam) {
+	case 0xf:
+		if (pvt->ext_model >= K8_REV_F)
+			goto dflt;
+
 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
-	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {
+		break;
+
+	case 0x15:
+		if (pvt->model != 0x30)
+			goto dflt;
+
 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
-	} else {
+		break;
+
+dflt:
+	default:
 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
 	}

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

  reply index

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-31 23:45 [PATCH 0/8] AMD64 EDAC fixes for v5.2 Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 1/8] EDAC/amd64: Fix number of DIMMs and Chip Select bases/masks on Family17h Ghannam, Yazen
2019-06-13 13:58   ` Borislav Petkov
2019-06-13 21:00     ` Ghannam, Yazen
2019-06-17 13:37       ` Borislav Petkov [this message]
2019-05-31 23:45 ` [PATCH 2/8] EDAC/amd64: Support more than two controllers for chip selects handling Ghannam, Yazen
2019-06-13 14:17   ` Borislav Petkov
2019-06-13 20:58     ` Ghannam, Yazen
2019-06-13 22:22       ` Borislav Petkov
2019-06-14 14:14         ` Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 3/8] EDAC/amd64: Recognize DRAM device type with EDAC_CTL_CAP Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 5/8] EDAC/amd64: Find Chip Select memory size using Address Mask Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 4/8] EDAC/amd64: Initialize DIMM info for systems with more than two channels Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 7/8] EDAC/amd64: Cache secondary Chip Select registers Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 6/8] EDAC/amd64: Decode syndrome before translating address Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 8/8] EDAC/amd64: Support Asymmetric Dual-Rank DIMMs Ghannam, Yazen

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