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Thu, 23 Jan 2020 09:03:09 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::b96d:5663:6402:82ea]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::b96d:5663:6402:82ea%7]) with mapi id 15.20.2644.028; Thu, 23 Jan 2020 09:03:09 +0000 Received: from rric.localdomain (31.208.96.227) by HE1PR0902CA0010.eurprd09.prod.outlook.com (2603:10a6:3:e5::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2644.20 via Frontend Transport; Thu, 23 Jan 2020 09:03:07 +0000 From: Robert Richter To: Borislav Petkov , Mauro Carvalho Chehab , Tony Luck CC: James Morse , Aristeu Rozanski , Robert Richter , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH v3 10/10] EDAC/mc: Remove per layer counters Thread-Topic: [PATCH v3 10/10] EDAC/mc: Remove per layer counters Thread-Index: AQHV0cvu7j4bgx3XFUyxLBDaaQwKHw== Date: Thu, 23 Jan 2020 09:03:09 +0000 Message-ID: <20200123090210.26933-11-rrichter@marvell.com> References: <20200123090210.26933-1-rrichter@marvell.com> In-Reply-To: <20200123090210.26933-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR0902CA0010.eurprd09.prod.outlook.com (2603:10a6:3:e5::20) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:165::10) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [31.208.96.227] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1e4a2c63-a88d-4ac9-9c53-08d79fe3111e x-ms-traffictypediagnostic: MN2PR18MB3247: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2089; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 1e4a2c63-a88d-4ac9-9c53-08d79fe3111e X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Jan 2020 09:03:09.2364 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: kLTF2r+UtY/Xh1yf2cM4xPHbUKUEXZ1Hrkd+nM9l/yjgmbJdAWCcVQQzpsgbjjc4pRidC6bjk1SH30+WIhYctQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3247 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.572 definitions=2020-01-22_08:2020-01-22,2020-01-22 signatures=0 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Looking at how mci->{ue,ce}_per_layer[EDAC_MAX_LAYERS] is used, it turns out that only the leaves in the memory hierarchy are consumed (in sysfs), but not the intermediate layers, e.g.: count =3D dimm->mci->ce_per_layer[dimm->mci->n_layers-1][dimm->idx]; These unused counters only add complexity, remove them. The error counter values are directly stored in struct dimm_info now. Signed-off-by: Robert Richter Acked-by: Aristeu Rozanski --- drivers/edac/edac_mc.c | 65 +++++++++--------------------------- drivers/edac/edac_mc_sysfs.c | 20 +++++------ include/linux/edac.h | 4 ++- 3 files changed, 26 insertions(+), 63 deletions(-) diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 60639def8697..fbd9faa5c0f9 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -451,11 +451,9 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num= , { struct mem_ctl_info *mci; struct edac_mc_layer *layer; - u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; - unsigned int idx, size, tot_dimms =3D 1, count =3D 1; - unsigned int tot_csrows =3D 1, tot_channels =3D 1, tot_errcount =3D 0; + unsigned int idx, size, tot_dimms =3D 1; + unsigned int tot_csrows =3D 1, tot_channels =3D 1; void *pvt, *ptr =3D NULL; - int i; bool per_rank =3D false; =20 if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers =3D=3D 0)) @@ -482,19 +480,10 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_nu= m, * stringent as what the compiler would provide if we could simply * hardcode everything into a single struct. */ - mci =3D edac_align_ptr(&ptr, sizeof(*mci), 1); - layer =3D edac_align_ptr(&ptr, sizeof(*layer), n_layers); - for (i =3D 0; i < n_layers; i++) { - count *=3D layers[i].size; - edac_dbg(4, "errcount layer %d size %d\n", i, count); - ce_per_layer[i] =3D edac_align_ptr(&ptr, sizeof(u32), count); - ue_per_layer[i] =3D edac_align_ptr(&ptr, sizeof(u32), count); - tot_errcount +=3D 2 * count; - } - - edac_dbg(4, "allocating %d error counters\n", tot_errcount); - pvt =3D edac_align_ptr(&ptr, sz_pvt, 1); - size =3D ((unsigned long)pvt) + sz_pvt; + mci =3D edac_align_ptr(&ptr, sizeof(*mci), 1); + layer =3D edac_align_ptr(&ptr, sizeof(*layer), n_layers); + pvt =3D edac_align_ptr(&ptr, sz_pvt, 1); + size =3D ((unsigned long)pvt) + sz_pvt; =20 edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)= \n", size, @@ -513,10 +502,6 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num= , * rather than an imaginary chunk of memory located at address 0. */ layer =3D (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)= ); - for (i =3D 0; i < n_layers; i++) { - mci->ce_per_layer[i] =3D (u32 *)((char *)mci + ((unsigned long)ce_per_la= yer[i])); - mci->ue_per_layer[i] =3D (u32 *)((char *)mci + ((unsigned long)ue_per_la= yer[i])); - } pvt =3D sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; =20 /* setup index and various internal pointers */ @@ -951,48 +936,28 @@ static void edac_inc_ce_error(struct edac_raw_error_d= esc *e) { struct mem_ctl_info *mci =3D error_desc_to_mci(e); int pos[EDAC_MAX_LAYERS] =3D { e->top_layer, e->mid_layer, e->low_layer }= ; - int i, index =3D 0; + struct dimm_info *dimm =3D edac_get_dimm(mci, pos[0], pos[1], pos[2]); =20 mci->ce_mc +=3D e->error_count; =20 - if (pos[0] < 0) { + if (dimm) + dimm->ce_count +=3D e->error_count; + else mci->ce_noinfo_count +=3D e->error_count; - return; - } - - for (i =3D 0; i < mci->n_layers; i++) { - if (pos[i] < 0) - break; - index +=3D pos[i]; - mci->ce_per_layer[i][index] +=3D e->error_count; - - if (i < mci->n_layers - 1) - index *=3D mci->layers[i + 1].size; - } } =20 static void edac_inc_ue_error(struct edac_raw_error_desc *e) { struct mem_ctl_info *mci =3D error_desc_to_mci(e); int pos[EDAC_MAX_LAYERS] =3D { e->top_layer, e->mid_layer, e->low_layer }= ; - int i, index =3D 0; + struct dimm_info *dimm =3D edac_get_dimm(mci, pos[0], pos[1], pos[2]); =20 mci->ue_mc +=3D e->error_count; =20 - if (pos[0] < 0) { + if (dimm) + dimm->ue_count +=3D e->error_count; + else mci->ue_noinfo_count +=3D e->error_count; - return; - } - - for (i =3D 0; i < mci->n_layers; i++) { - if (pos[i] < 0) - break; - index +=3D pos[i]; - mci->ue_per_layer[i][index] +=3D e->error_count; - - if (i < mci->n_layers - 1) - index *=3D mci->layers[i + 1].size; - } } =20 static void edac_ce_error(struct edac_raw_error_desc *e) @@ -1139,7 +1104,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_= type type, /* * Check if the event report is consistent and if the memory * location is known. If it is known, the DIMM(s) label info - * will be filled and the per-layer error counters will be + * will be filled and the DIMM's error counters will be * incremented. */ for (i =3D 0; i < mci->n_layers; i++) { diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 408bace699dc..20657530a108 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -551,10 +551,8 @@ static ssize_t dimmdev_ce_count_show(struct device *de= v, char *data) { struct dimm_info *dimm =3D to_dimm(dev); - u32 count; =20 - count =3D dimm->mci->ce_per_layer[dimm->mci->n_layers-1][dimm->idx]; - return sprintf(data, "%u\n", count); + return sprintf(data, "%u\n", dimm->ce_count); } =20 static ssize_t dimmdev_ue_count_show(struct device *dev, @@ -562,10 +560,8 @@ static ssize_t dimmdev_ue_count_show(struct device *de= v, char *data) { struct dimm_info *dimm =3D to_dimm(dev); - u32 count; =20 - count =3D dimm->mci->ue_per_layer[dimm->mci->n_layers-1][dimm->idx]; - return sprintf(data, "%u\n", count); + return sprintf(data, "%u\n", dimm->ue_count); } =20 /* dimm/rank attribute files */ @@ -661,7 +657,9 @@ static ssize_t mci_reset_counters_store(struct device *= dev, const char *data, size_t count) { struct mem_ctl_info *mci =3D to_mci(dev); - int cnt, row, chan, i; + struct dimm_info *dimm; + int row, chan; + mci->ue_mc =3D 0; mci->ce_mc =3D 0; mci->ue_noinfo_count =3D 0; @@ -677,11 +675,9 @@ static ssize_t mci_reset_counters_store(struct device = *dev, ri->channels[chan]->ce_count =3D 0; } =20 - cnt =3D 1; - for (i =3D 0; i < mci->n_layers; i++) { - cnt *=3D mci->layers[i].size; - memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); - memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); + mci_for_each_dimm(mci, dimm) { + dimm->ue_count =3D 0; + dimm->ce_count =3D 0; } =20 mci->start_time =3D jiffies; diff --git a/include/linux/edac.h b/include/linux/edac.h index 815f246e0abd..0f20b986b0ab 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -383,6 +383,9 @@ struct dimm_info { unsigned int csrow, cschannel; /* Points to the old API data */ =20 u16 smbios_handle; /* Handle for SMBIOS type 17 */ + + u32 ce_count; + u32 ue_count; }; =20 /** @@ -559,7 +562,6 @@ struct mem_ctl_info { */ u32 ce_noinfo_count, ue_noinfo_count; u32 ue_mc, ce_mc; - u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; =20 struct completion complete; =20 --=20 2.20.1