Hi Dhananjay,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on ras/edac-for-next]
[also build test ERROR on next-20200225]
[cannot apply to v5.6-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Dhananjay-Kangude/Add-EDAC-support-for-Cadence-ddr-controller/20200225-185633
base:   https://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac-for-next
config: arm64-allyesconfig (attached as .config)
compiler: clang version 11.0.0 (git://gitmirror/llvm_project 7f9f027c62623bff79730cd30d1a8a534e2ddb06)
reproduce:
        # FIXME the reproduce steps for clang is not ready yet

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

>> drivers/edac/cadence_edac.c:179:9: error: implicit declaration of function 'EDAC_DIMM_PTR' [-Werror,-Wimplicit-function-declaration]
           dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0);
                  ^
>> drivers/edac/cadence_edac.c:179:7: warning: incompatible integer to pointer conversion assigning to 'struct dimm_info *' from 'int' [-Wint-conversion]
           dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0);
                ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/edac/cadence_edac.c:476:17: warning: unused variable 'root' [-Wunused-variable]
           struct dentry *root;
                          ^
   2 warnings and 1 error generated.

vim +/EDAC_DIMM_PTR +179 drivers/edac/cadence_edac.c

   159	
   160	/**
   161	 * init_mem_layout -  Set address Map as per the mc design.
   162	 * @mci:   memory controller information.
   163	 *
   164	 * Set Address Map as per mc instance .
   165	 *
   166	 * Return: none.
   167	 */
   168	static void init_mem_layout(struct mem_ctl_info *mci)
   169	{
   170		struct cdns_edac_priv_data *priv = mci->pvt_info;
   171		struct csrow_info *csi;
   172		struct dimm_info *dimm;
   173		struct sysinfo inf;
   174		enum mem_type mtype;
   175		u32 val, width;
   176		u32 size, row;
   177		u8 j;
   178	
 > 179		dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0);
   180	
   181		si_meminfo(&inf);
   182		for (row = 0; row < mci->nr_csrows; row++) {
   183			csi = mci->csrows[row];
   184			size = inf.totalram * inf.mem_unit;
   185	
   186			for (j = 0; j < csi->nr_channels; j++) {
   187				dimm            = csi->channels[j]->dimm;
   188				dimm->edac_mode = EDAC_FLAG_SECDED;
   189				/* Get memory type by reading hw registers*/
   190				val = readl(priv->reg + DDR_CTL_MEM_TYPE_REG);
   191				mtype = val & ECC_CTL_MTYPE_MASK;
   192	
   193				if (mtype == MEM_TYPE_DDR4)
   194					dimm->mtype = MEM_DDR4;
   195				else
   196					dimm->mtype = MEM_EMPTY;
   197	
   198				/*Get EDAC devtype width for the current mc*/
   199				width = (readl(priv->reg + DDR_CTL_MEM_WIDTH_REG) &
   200					       CTL_MEM_MAX_WIDTH_MASK);
   201				switch (width) {
   202				case WDTH_16:
   203					dimm->dtype  = DEV_X2;
   204					break;
   205				case WDTH_32:
   206					dimm->dtype  = DEV_X4;
   207					break;
   208				case WDTH_64:
   209					dimm->dtype  = DEV_X8;
   210					break;
   211				default:
   212					dimm->dtype = DEV_UNKNOWN;
   213				}
   214	
   215				dimm->nr_pages  = (size >> PAGE_SHIFT) /
   216						   csi->nr_channels;
   217				dimm->grain     = CDNS_EDAC_ERR_GRAIN;
   218			}
   219		}
   220	}
   221	

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