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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id a30sm964052otc.79.2020.02.26.09.24.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 09:24:59 -0800 (PST) Received: (nullmailer pid 5983 invoked by uid 1000); Wed, 26 Feb 2020 17:24:57 -0000 Date: Wed, 26 Feb 2020 11:24:57 -0600 From: Rob Herring To: sherry sun Cc: bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, james.morse@arm.com, rrichter@marvell.com, michal.simek@xilinx.com, shawnguo@kernel.org, s.hauer@pengutronix.de, mark.rutland@arm.com, linux-edac@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com, frank.li@nxp.com Subject: Re: [PATCH 1/3] dt-bindings: memory-controllers: Add i.MX8MP DDRC binding doc Message-ID: <20200226172457.GA3267@bogus> References: <1582267156-20189-1-git-send-email-sherry.sun@nxp.com> <1582267156-20189-2-git-send-email-sherry.sun@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1582267156-20189-2-git-send-email-sherry.sun@nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On Fri, Feb 21, 2020 at 02:39:14PM +0800, sherry sun wrote: > From: Sherry Sun > > Add documentation for i.MX8MP DDRC binding based on synopsys_edac doc, > which use the same memory-controller IP. > > Signed-off-by: Sherry Sun > --- > .../devicetree/bindings/memory-controllers/synopsys.txt | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > index 9d32762c47e1..5c03959a451f 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > @@ -6,16 +6,20 @@ bus width configurations. > The Zynq DDR ECC controller has an optional ECC support in half-bus width > (16-bit) configuration. > > -These both ECC controllers correct single bit ECC errors and detect double bit > +The i.MX8MP DDR ECC controller has an ECC support in 64-bit bus width > +configurations. > + > +These all ECC controllers correct single bit ECC errors and detect double bit All the ECC... With that, Reviewed-by: Rob Herring > ECC errors. > > Required properties: > - compatible: One of: > - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller > - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller > + - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller > - reg: Should contain DDR controller registers location and length. > > -Required properties for "xlnx,zynqmp-ddrc-2.40a": > +Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc": > - interrupts: Property with a value describing the interrupt number. > > Example: > -- > 2.17.1 >