linux-edac.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Dhananjay Kangude <dkangude@cadence.com>
To: <linux-edac@vger.kernel.org>
Cc: <bp@alien8.de>, <mchehab@kernel.org>, <tony.luck@intel.com>,
	<james.morse@arm.com>, <linux-kernel@vger.kernel.org>,
	<mparab@cadence.com>, <robh+dt@kernel.org>,
	<devicetree@vger.kernel.org>,
	Dhananjay Kangude <dkangude@cadence.com>
Subject: [PATCH v1 0/2] Add EDAC support for Cadence ddr controller
Date: Fri, 28 Feb 2020 10:43:20 +0100	[thread overview]
Message-ID: <20200228094322.13617-1-dkangude@cadence.com> (raw)

These patches add new edac driver for Cadence ddr memory controller.
Cadence controller detects single(CE) and double(UE) bit errors during
memory operations(RMW). DDR controller raised the interrupt on detection
of the ecc error event and fill the data into registers. Driver handle
the interrupt event and notify edac subsystem about ecc errors.

Changes since v1:
=================
- Made predefined arrays as static
 Fixes: 201447a5db9b ("EDAC/Cadence:Add EDAC driver for cadence memory controller")
- Replace macro 'EDAC_DIMM_PTR' with newly introduce function
- Removed unused variable root

Dhananjay Kangude (2):
  EDAC/Cadence:Add EDAC driver for cadence memory controller
  dt-bindings: edac: Add cadence ddr mc support

 .../devicetree/bindings/edac/cdns,ddr-edac.yaml    |  59 ++
 drivers/edac/Kconfig                               |   7 +
 drivers/edac/Makefile                              |   1 +
 drivers/edac/cadence_edac.c                        | 615 +++++++++++++++++++++
 4 files changed, 682 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
 create mode 100644 drivers/edac/cadence_edac.c


base-commit: ffa9a9758be2793d11b0c51bc2845f7dd200e261
-- 
2.15.0


             reply	other threads:[~2020-02-28  9:43 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-28  9:43 Dhananjay Kangude [this message]
2020-02-28  9:43 ` [PATCH v1 1/2] EDAC/Cadence:Add EDAC driver for cadence memory controller Dhananjay Kangude
2020-03-20 17:41   ` Borislav Petkov
2020-02-28  9:43 ` [PATCH v1 2/2] dt-bindings: edac: Add cadence ddr mc support Dhananjay Kangude
2020-03-10 18:44   ` Rob Herring

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200228094322.13617-1-dkangude@cadence.com \
    --to=dkangude@cadence.com \
    --cc=bp@alien8.de \
    --cc=devicetree@vger.kernel.org \
    --cc=james.morse@arm.com \
    --cc=linux-edac@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mchehab@kernel.org \
    --cc=mparab@cadence.com \
    --cc=robh+dt@kernel.org \
    --cc=tony.luck@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).