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From: Dhananjay Kangude <dkangude@cadence.com>
To: <linux-edac@vger.kernel.org>
Cc: <bp@alien8.de>, <mchehab@kernel.org>, <tony.luck@intel.com>,
	<james.morse@arm.com>, <linux-kernel@vger.kernel.org>,
	<mparab@cadence.com>, <robh+dt@kernel.org>,
	<devicetree@vger.kernel.org>,
	Dhananjay Kangude <dkangude@cadence.com>
Subject: [PATCH v4 1/2] dt-bindings: edac: Add cadence ddr mc support
Date: Fri, 24 Apr 2020 10:31:54 +0200
Message-ID: <20200424083155.30918-2-dkangude@cadence.com> (raw)
In-Reply-To: <20200424083155.30918-1-dkangude@cadence.com>

Add documentation for cadence ddr memory controller EDAC DTS bindings

Signed-off-by: Dhananjay Kangude <dkangude@cadence.com>
---
 .../devicetree/bindings/edac/cdns,ddr-edac.yaml    |   45 ++++++++++++++++++++
 1 files changed, 45 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml

diff --git a/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
new file mode 100644
index 0000000..198e60d
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/cdns,ddr-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence DDR IP with ECC support (EDAC)
+
+description:
+  This binding describes the Cadence DDR/LPDDR IP with ECC feature enabled
+  to detect and correct CE/UE errors.
+
+maintainers:
+  - Dhananjay Kangdue <dkangude@cadence.com>
+
+properties:
+  compatible:
+    items:
+      - cdns,ddr4-mc-edac
+
+  reg:
+    items:
+      - description:
+          Register block of DDR/LPDDR apb registers up to mapped area.
+          Mapped area contains the register set for memory controller,
+          phy and PI module register set doesn't part of this mapping.
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    edac: edac@fd100000 {
+        compatible = "cdns,ddr4-mc-edac";
+        reg = <0xfd100000 0x4000>;
+        interrupts = <0x00 0x01 0x04>;
+    };
+...
-- 
1.7.1


  reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-24  8:31 [PATCH v4 0/2] Add EDAC support for Cadence ddr controller Dhananjay Kangude
2020-04-24  8:31 ` Dhananjay Kangude [this message]
2020-04-27 21:31   ` [PATCH v4 1/2] dt-bindings: edac: Add cadence ddr mc support Rob Herring
2020-04-24  8:31 ` [PATCH v4 2/2] EDAC/Cadence:Add EDAC driver for cadence memory controller Dhananjay Kangude
2020-05-11 17:44   ` James Morse

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