Linux-EDAC Archive on lore.kernel.org
 help / color / Atom feed
From: Rob Herring <robh@kernel.org>
To: Yash Shah <yash.shah@sifive.com>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com, bp@alien8.de,
	mchehab@kernel.org, tony.luck@intel.com, aou@eecs.berkeley.edu,
	james.morse@arm.com, rrichter@marvell.com,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
	sachin.ghadi@sifive.com
Subject: Re: [PATCH v2 0/3] SiFive DDR controller and EDAC support
Date: Tue, 15 Sep 2020 09:22:01 -0600
Message-ID: <20200915152201.GA1940827@bogus> (raw)
In-Reply-To: <1599457679-8947-1-git-send-email-yash.shah@sifive.com>

On Mon, Sep 07, 2020 at 11:17:56AM +0530, Yash Shah wrote:
> The series add supports for SiFive DDR controller driver. This driver
> is use to manage the Cadence DDR controller present in SiFive SoCs.
> Currently it manages only the EDAC feature of the DDR controller.
> The series also adds Memory controller EDAC support for SiFive platform.
> It register for notifier event from SiFive DDR controller driver.

This is an odd split and notifiers aren't a great interface. Why not 
just combine these? Is there some other DDR controller functionality 
planned for the driver? 

FYI, highbank_mc_edac.c is also a Cadence controller. IIRC, the register 
layout changes for every customer/design.

Rob

      parent reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-07  5:47 Yash Shah
2020-09-07  5:47 ` [PATCH v2 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs Yash Shah
2020-09-15 15:24   ` Rob Herring
2020-09-07  5:47 ` [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver Yash Shah
2020-09-07  5:54   ` Randy Dunlap
2020-09-07  6:11   ` Christoph Hellwig
2020-09-09  3:12     ` Palmer Dabbelt
2020-09-09  3:56       ` Yash Shah
2020-09-09  6:00       ` Christoph Hellwig
2020-09-09 20:31         ` Palmer Dabbelt
2020-09-17  9:56       ` Dhananjay Vilasrao Kangude
2020-09-07  5:47 ` [PATCH v2 3/3] EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs Yash Shah
2020-09-23 17:10   ` Borislav Petkov
2020-09-15 15:22 ` Rob Herring [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200915152201.GA1940827@bogus \
    --to=robh@kernel.org \
    --cc=aou@eecs.berkeley.edu \
    --cc=bp@alien8.de \
    --cc=devicetree@vger.kernel.org \
    --cc=james.morse@arm.com \
    --cc=linux-edac@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=mchehab@kernel.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=rrichter@marvell.com \
    --cc=sachin.ghadi@sifive.com \
    --cc=tony.luck@intel.com \
    --cc=yash.shah@sifive.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Linux-EDAC Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-edac/0 linux-edac/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-edac linux-edac/ https://lore.kernel.org/linux-edac \
		linux-edac@vger.kernel.org
	public-inbox-index linux-edac

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-edac


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git