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From: Borislav Petkov <bp@alien8.de>
To: Yash Shah <yash.shah@sifive.com>
Cc: robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com,
	mchehab@kernel.org, tony.luck@intel.com, aou@eecs.berkeley.edu,
	james.morse@arm.com, rrichter@marvell.com,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
	sachin.ghadi@sifive.com
Subject: Re: [PATCH v2 3/3] EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs
Date: Wed, 23 Sep 2020 19:10:13 +0200
Message-ID: <20200923171013.GS28545@zn.tnic> (raw)
In-Reply-To: <1599457679-8947-4-git-send-email-yash.shah@sifive.com>

On Mon, Sep 07, 2020 at 11:17:59AM +0530, Yash Shah wrote:
> Add Memory controller EDAC support to the SiFive platform EDAC driver.
> It registers for ECC notifier events from the memory controller.
> 
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>

Reviewed-by is usually enough and stronger than Acked-by. See sections

12) When to use Acked-by:, Cc:, and Co-developed-by:
13) Using Reported-by:, Tested-by:, Reviewed-by:, Suggested-by: and Fixes:

in Documentation/process/submitting-patches.rst.

With that addressed:

Acked-by: Borislav Petkov <bp@suse.de>

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

  reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-07  5:47 [PATCH v2 0/3] SiFive DDR controller and EDAC support Yash Shah
2020-09-07  5:47 ` [PATCH v2 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs Yash Shah
2020-09-15 15:24   ` Rob Herring
2020-09-07  5:47 ` [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver Yash Shah
2020-09-07  5:54   ` Randy Dunlap
2020-09-07  6:11   ` Christoph Hellwig
2020-09-09  3:12     ` Palmer Dabbelt
2020-09-09  3:56       ` Yash Shah
2020-09-09  6:00       ` Christoph Hellwig
2020-09-09 20:31         ` Palmer Dabbelt
2020-09-17  9:56       ` Dhananjay Vilasrao Kangude
2020-09-07  5:47 ` [PATCH v2 3/3] EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs Yash Shah
2020-09-23 17:10   ` Borislav Petkov [this message]
2020-09-15 15:22 ` [PATCH v2 0/3] SiFive DDR controller and EDAC support Rob Herring

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