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* [PATCH v2 0/8] AMD MCA Address Translation Updates
@ 2020-09-03 20:01 Yazen Ghannam
  2020-09-03 20:01 ` [PATCH v2 1/8] x86/CPU/AMD: Save NodeId on AMD-based systems Yazen Ghannam
                   ` (7 more replies)
  0 siblings, 8 replies; 31+ messages in thread
From: Yazen Ghannam @ 2020-09-03 20:01 UTC (permalink / raw)
  To: linux-edac
  Cc: Yazen Ghannam, linux-kernel, tony.luck, x86,
	Smita.KoralahalliChannabasappa

From: Yazen Ghannam <yazen.ghannam@amd.com>

This patchset includes updates for the MCA Address Translation process
on recent AMD systems.

Patches 1 & 3:
Fixes an input to the address translation function. The translation
requires a physical Die ID (NodeId in AMD documentation) rather than a
logicial NUMA node ID. This is because the physical and logical nodes
may not always match.

Patch 2:
Removes a function that is no longer needed with Patch 1.

Patches 4-7:
Code cleanup in preparation for Patch 8.

Patch 8:
Add translation support for new memory interleaving options available in
Rome systems. The patch is based on the latest AMD reference code for
the address translation.

Patches 6-8 have checkpatch warnings about long lines, but I kept the
long lines for readability.

Thanks,
Yazen

Link:
https://lkml.kernel.org/r/20200814191449.183998-1-Yazen.Ghannam@amd.com

v1 -> v2:
* Save the AMD NodeId value in struct cpuinfo_x86 rather than use a
  local value in MCA code.
* Include code cleanup for AMD MCA Address Translation function before
  adding new functionality.

Muralidhara M K (1):
  x86/MCE/AMD Support new memory interleaving modes during address
    translation

Yazen Ghannam (7):
  x86/CPU/AMD: Save NodeId on AMD-based systems
  x86/CPU/AMD: Remove amd_get_nb_id()
  EDAC/mce_amd: Use struct cpuinfo_x86.node_id for NodeId
  x86/MCE/AMD: Use defines for register addresses in translation code
  x86/MCE/AMD: Use macros to get bitfields in translation code
  x86/MCE/AMD: Drop tmp variable in translation code
  x86/MCE/AMD: Group register reads in translation code

 arch/x86/events/amd/core.c       |   2 +-
 arch/x86/include/asm/cacheinfo.h |   4 +-
 arch/x86/include/asm/processor.h |   3 +-
 arch/x86/kernel/amd_nb.c         |   4 +-
 arch/x86/kernel/cpu/amd.c        |  17 +-
 arch/x86/kernel/cpu/cacheinfo.c  |   8 +-
 arch/x86/kernel/cpu/hygon.c      |  11 +-
 arch/x86/kernel/cpu/mce/amd.c    | 284 ++++++++++++++++++++++---------
 arch/x86/kernel/cpu/mce/inject.c |   4 +-
 drivers/edac/amd64_edac.c        |   4 +-
 drivers/edac/mce_amd.c           |   4 +-
 11 files changed, 233 insertions(+), 112 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 31+ messages in thread

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Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-03 20:01 [PATCH v2 0/8] AMD MCA Address Translation Updates Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 1/8] x86/CPU/AMD: Save NodeId on AMD-based systems Yazen Ghannam
2020-09-09 18:06   ` Borislav Petkov
2020-09-09 20:17     ` Yazen Ghannam
2020-09-10 10:14       ` Borislav Petkov
2020-09-14 19:20         ` Yazen Ghannam
2020-09-15  8:35           ` Borislav Petkov
2020-09-16 19:51             ` Yazen Ghannam
2020-09-17 10:37               ` Borislav Petkov
2020-09-17 16:20                 ` Yazen Ghannam
2020-09-17 16:40                   ` Borislav Petkov
2020-09-17 19:44                     ` Yazen Ghannam
2020-09-17 20:10                       ` Borislav Petkov
2020-09-03 20:01 ` [PATCH v2 2/8] x86/CPU/AMD: Remove amd_get_nb_id() Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 3/8] EDAC/mce_amd: Use struct cpuinfo_x86.node_id for NodeId Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 4/8] x86/MCE/AMD: Use defines for register addresses in translation code Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 5/8] x86/MCE/AMD: Use macros to get bitfields " Yazen Ghannam
2020-09-21 13:58   ` Borislav Petkov
2020-09-03 20:01 ` [PATCH v2 6/8] x86/MCE/AMD: Drop tmp variable " Yazen Ghannam
2020-09-23  8:05   ` Borislav Petkov
2020-09-23 16:05     ` Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 7/8] x86/MCE/AMD: Group register reads " Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 8/8] x86/MCE/AMD Support new memory interleaving modes during address translation Yazen Ghannam
2020-09-23  8:20   ` Borislav Petkov
2020-09-23 16:25     ` Yazen Ghannam
2020-09-25  7:22       ` Borislav Petkov
2020-09-25 19:51         ` Yazen Ghannam
2020-09-28  9:47           ` Borislav Petkov
2020-09-28 15:53             ` Yazen Ghannam
2020-09-28 18:14               ` Borislav Petkov
2020-09-29 13:21                 ` Yazen Ghannam

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