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From: Yazen Ghannam <Yazen.Ghannam@amd.com>
To: linux-edac@vger.kernel.org
Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>,
	linux-kernel@vger.kernel.org, bp@alien8.de,
	Smita.KoralahalliChannabasappa@amd.com, wgh@torlan.ru
Subject: [PATCH] EDAC/AMD64: Update scrub register addresses for newer models
Date: Sat, 16 Jan 2021 14:33:53 +0000	[thread overview]
Message-ID: <20210116143353.7576-1-Yazen.Ghannam@amd.com> (raw)

From: Yazen Ghannam <yazen.ghannam@amd.com>

The Family 17h scrubber registers moved to different offset starting
with Model 30h. The new register offsets are used for all currently
available models since then.

Use the new register addresses as the defaults.

Set the proper scrub register addresses during module init for older
models.

Reported-by: WGH <wgh@torlan.ru>
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 drivers/edac/amd64_edac.c | 23 ++++++++++++++++++-----
 drivers/edac/amd64_edac.h |  2 ++
 2 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 9868f95a5622..b324b1589e5a 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -167,6 +167,10 @@ static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
  * other archs, we might not have access to the caches directly.
  */
 
+static struct {
+	u32 base, limit;
+} f17h_scrub_regs = {F17H_M30H_SCR_BASE_ADDR, F17H_M30H_SCR_LIMIT_ADDR};
+
 static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval)
 {
 	/*
@@ -176,10 +180,10 @@ static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval)
 	 */
 	if (scrubval >= 0x5 && scrubval <= 0x14) {
 		scrubval -= 0x5;
-		pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF);
-		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1);
+		pci_write_bits32(pvt->F6, f17h_scrub_regs.limit, scrubval, 0xF);
+		pci_write_bits32(pvt->F6, f17h_scrub_regs.base, 1, 0x1);
 	} else {
-		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1);
+		pci_write_bits32(pvt->F6, f17h_scrub_regs.base, 0, 0x1);
 	}
 }
 /*
@@ -257,9 +261,9 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
 	u32 scrubval = 0;
 
 	if (pvt->umc) {
-		amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
+		amd64_read_pci_cfg(pvt->F6, f17h_scrub_regs.base, &scrubval);
 		if (scrubval & BIT(0)) {
-			amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
+			amd64_read_pci_cfg(pvt->F6, f17h_scrub_regs.limit, &scrubval);
 			scrubval &= 0xF;
 			scrubval += 0x5;
 		} else {
@@ -3568,6 +3572,14 @@ f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
 	}
 }
 
+static void f17h_set_scrub_regs(struct amd64_pvt *pvt)
+{
+	if ((pvt->fam == 0x17 && pvt->model < 0x30) || pvt->fam == 0x18) {
+		f17h_scrub_regs.base = F17H_SCR_BASE_ADDR;
+		f17h_scrub_regs.limit = F17H_SCR_LIMIT_ADDR;
+	}
+}
+
 static void setup_mci_misc_attrs(struct mem_ctl_info *mci)
 {
 	struct amd64_pvt *pvt = mci->pvt_info;
@@ -3577,6 +3589,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci)
 
 	if (pvt->umc) {
 		f17h_determine_edac_ctl_cap(mci, pvt);
+		f17h_set_scrub_regs(pvt);
 	} else {
 		if (pvt->nbcap & NBCAP_SECDED)
 			mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 85aa820bc165..4606f72f4258 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -213,6 +213,8 @@
 #define F15H_M60H_SCRCTRL		0x1C8
 #define F17H_SCR_BASE_ADDR		0x48
 #define F17H_SCR_LIMIT_ADDR		0x4C
+#define F17H_M30H_SCR_BASE_ADDR		0x40
+#define F17H_M30H_SCR_LIMIT_ADDR	0x44
 
 /*
  * Function 3 - Misc Control
-- 
2.25.1


             reply	other threads:[~2021-01-16 17:10 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-16 14:33 Yazen Ghannam [this message]
2021-01-18  1:30 ` [PATCH] EDAC/AMD64: Update scrub register addresses for newer models WGH
2021-01-20 14:35   ` Yazen Ghannam
2021-01-18 19:31 ` Borislav Petkov
2021-01-20 14:41   ` Yazen Ghannam
2021-01-20 14:50     ` Borislav Petkov

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