Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property

[Sascha Hauer <s.hauer@pengutronix.de>]

On Mon, Feb 01, 2021 at 12:57:53PM +0100, Sascha Hauer wrote:
> Some CPUs like the Cortex-A53 and Cortex-A57 have Error Detection And
> Correction (EDAC) support on their L1 and L2 caches. This is implemented
> in implementation defined registers, so usage of this functionality is
> not safe in virtualized environments or when EL3 already uses these
> registers.
> This patch adds a edac-enabled flag which can be explicitly set when
> EDAC can be used.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>  drivers/edac/cortex_arm64_l1_l2.c               | 7 +++++--
>  2 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index f02fd10de604..80dcf90f3e78 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -269,6 +269,12 @@ properties:
>        For PSCI based platforms, the name corresponding to the index of the PSCI
>        PM domain provider, must be "psci".
>  
> +  edac-enabled:
> +    $ref: '/schemas/types.yaml#/definitions/flag'
> +    description:
> +      Some CPUs support Error Detection And Correction (EDAC) on their L1 and
> +      L2 caches. This flag marks this function as usable.
> +
>    qcom,saw:
>      $ref: '/schemas/types.yaml#/definitions/phandle'
>      description: |
> diff --git a/drivers/edac/cortex_arm64_l1_l2.c b/drivers/edac/cortex_arm64_l1_l2.c
> index 3b1e2f3ccab6..6d5355bae80c 100644
> --- a/drivers/edac/cortex_arm64_l1_l2.c
> +++ b/drivers/edac/cortex_arm64_l1_l2.c
> @@ -190,8 +190,11 @@ static int __init cortex_arm64_edac_driver_init(void)
>  	for_each_possible_cpu(cpu) {
>  		np = of_get_cpu_node(cpu, NULL);
>  
> -		if (of_match_node(cortex_arm64_edac_of_match, np))
> -			cpumask_set_cpu(cpu, &compat_mask);
> +		if (!of_match_node(cortex_arm64_edac_of_match, np))
> +			continue;
> +		if (!of_property_read_bool(np, "edac-enabled"))
> +			continue;
> +		cpumask_set_cpu(cpu, &compat_mask);

Hum, this should be in patch 1/2 of course.

Sascha

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