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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: linux-edac@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org,
	tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com,
	Yazen Ghannam <yazen.ghannam@amd.com>
Subject: [PATCH v2 30/31] EDAC/amd64: Add support for address translation on DF3 systems
Date: Wed, 23 Jun 2021 19:20:01 +0000	[thread overview]
Message-ID: <20210623192002.3671647-31-yazen.ghannam@amd.com> (raw)
In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com>

DF3-based systems (Rome and later) support new interleaving modes and a
number of bit fields have changed or moved entirely. Add support for
these new modes and fields.

Refactoring should be minimal due to earlier changes, and most updates
will be additions.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20210507190140.18854-26-Yazen.Ghannam@amd.com

v1->v2:
* Moved from arch/x86 to EDAC.
* Use function pointers as needed.

 drivers/edac/amd64_edac.c | 189 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 187 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index aa8b8d0b319d..882ac3fbc832 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1059,9 +1059,11 @@ enum df_reg_names {
 	DRAM_BASE_ADDR,
 	DRAM_LIMIT_ADDR,
 	DRAM_OFFSET,
+	DF_GLOBAL_CTL,
 
 	/* Function 1 */
 	SYS_FAB_ID_MASK,
+	SYS_FAB_ID_MASK_1,
 };
 
 static struct df_reg df_regs[] = {
@@ -1075,14 +1077,23 @@ static struct df_reg df_regs[] = {
 	[DRAM_LIMIT_ADDR]	=	{0, 0x114},
 	/* D18F0x1B4 (DramOffset) */
 	[DRAM_OFFSET]		=	{0, 0x1B4},
+	/* D18F0x3F8 (DfGlobalCtrl) */
+	[DF_GLOBAL_CTL]		=	{0, 0x3F8},
 	/* D18F1x208 (SystemFabricIdMask) */
 	[SYS_FAB_ID_MASK]	=	{1, 0x208},
+	/* D18F1x20C (SystemFabricIdMask1) */
+	[SYS_FAB_ID_MASK_1]	=	{1, 0x20C},
 };
 
 /* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */
 enum intlv_modes {
 	NONE		= 0x00,
 	NOHASH_2CH	= 0x01,
+	NOHASH_4CH	= 0x03,
+	NOHASH_8CH	= 0x05,
+	HASH_COD4_2CH	= 0x0C,
+	HASH_COD2_4CH	= 0x0D,
+	HASH_COD1_8CH	= 0x0E,
 	DF2_HASH_2CH	= 0x21,
 };
 
@@ -1094,6 +1105,7 @@ struct addr_ctx {
 	u32 reg_base_addr;
 	u32 reg_limit_addr;
 	u32 reg_fab_id_mask0;
+	u32 reg_fab_id_mask1;
 	u16 cs_fabric_id;
 	u16 die_id_mask;
 	u16 socket_id_mask;
@@ -1105,6 +1117,7 @@ struct addr_ctx {
 	u8 intlv_num_dies;
 	u8 intlv_num_sockets;
 	u8 cs_id;
+	u8 node_id_shift;
 	int (*dehash_addr)(struct addr_ctx *ctx);
 	void (*make_space_for_cs_id)(struct addr_ctx *ctx);
 	void (*insert_cs_id)(struct addr_ctx *ctx);
@@ -1262,6 +1275,164 @@ struct data_fabric_ops df2_ops = {
 	.get_component_id_mask		=	&get_component_id_mask_df2,
 };
 
+static u64 get_hi_addr_offset_df3(struct addr_ctx *ctx)
+{
+	return (ctx->reg_dram_offset & GENMASK_ULL(31, 12)) << 16;
+}
+
+static void make_space_for_cs_id_cod_hash(struct addr_ctx *ctx)
+{
+	u8 num_intlv_bits = ctx->intlv_num_chan;
+
+	num_intlv_bits += ctx->intlv_num_sockets;
+	expand_bits(ctx->intlv_addr_bit, 1, &ctx->ret_addr);
+	if (num_intlv_bits > 1)
+		expand_bits(12, num_intlv_bits - 1, &ctx->ret_addr);
+}
+
+static void insert_cs_id_cod_hash(struct addr_ctx *ctx)
+{
+	ctx->ret_addr |= ((ctx->cs_id & 0x1) << ctx->intlv_addr_bit);
+	ctx->ret_addr |= ((ctx->cs_id & 0xE) << 11);
+}
+
+static int dehash_addr_df3(struct addr_ctx *ctx)
+{
+	u8 hashed_bit, intlv_ctl_64k, intlv_ctl_2M, intlv_ctl_1G;
+	u32 tmp;
+
+	if (amd_df_indirect_read(0, df_regs[DF_GLOBAL_CTL], DF_BROADCAST, &tmp))
+		return -EINVAL;
+
+	intlv_ctl_64k = !!((tmp >> 20) & 0x1);
+	intlv_ctl_2M  = !!((tmp >> 21) & 0x1);
+	intlv_ctl_1G  = !!((tmp >> 22) & 0x1);
+
+	hashed_bit =	(ctx->ret_addr >> 14) ^
+			((ctx->ret_addr >> 18) & intlv_ctl_64k) ^
+			((ctx->ret_addr >> 23) & intlv_ctl_2M) ^
+			((ctx->ret_addr >> 32) & intlv_ctl_1G) ^
+			(ctx->ret_addr >> ctx->intlv_addr_bit);
+
+	hashed_bit &= BIT(0);
+
+	if (hashed_bit != ((ctx->ret_addr >> ctx->intlv_addr_bit) & BIT(0)))
+		ctx->ret_addr ^= BIT(ctx->intlv_addr_bit);
+
+	if (ctx->intlv_mode != HASH_COD2_4CH &&
+	    ctx->intlv_mode != HASH_COD1_8CH)
+		return 0;
+
+	hashed_bit =	(ctx->ret_addr >> 12) ^
+			((ctx->ret_addr >> 16) & intlv_ctl_64k) ^
+			((ctx->ret_addr >> 21) & intlv_ctl_2M) ^
+			((ctx->ret_addr >> 30) & intlv_ctl_1G);
+
+	hashed_bit &= BIT(0);
+
+	if (hashed_bit != ((ctx->ret_addr >> 12) & BIT(0)))
+		ctx->ret_addr ^= BIT(12);
+
+	if (ctx->intlv_mode != HASH_COD1_8CH)
+		return 0;
+
+	hashed_bit =	(ctx->ret_addr >> 13) ^
+			((ctx->ret_addr >> 17) & intlv_ctl_64k) ^
+			((ctx->ret_addr >> 22) & intlv_ctl_2M) ^
+			((ctx->ret_addr >> 31) & intlv_ctl_1G);
+
+	hashed_bit &= BIT(0);
+
+	if (hashed_bit != ((ctx->ret_addr >> 13) & BIT(0)))
+		ctx->ret_addr ^= BIT(13);
+
+	return 0;
+}
+
+static int get_intlv_mode_df3(struct addr_ctx *ctx)
+{
+	ctx->intlv_mode = (ctx->reg_base_addr >> 2) & 0xF;
+
+	if (ctx->intlv_mode == HASH_COD4_2CH ||
+	    ctx->intlv_mode == HASH_COD2_4CH ||
+	    ctx->intlv_mode == HASH_COD1_8CH) {
+		ctx->make_space_for_cs_id = &make_space_for_cs_id_cod_hash;
+		ctx->insert_cs_id = &insert_cs_id_cod_hash;
+		ctx->dehash_addr = &dehash_addr_df3;
+	} else {
+		ctx->make_space_for_cs_id = &make_space_for_cs_id_simple;
+		ctx->insert_cs_id = &insert_cs_id_simple;
+	}
+
+	return 0;
+}
+
+static u8 get_intlv_addr_sel_df3(struct addr_ctx *ctx)
+{
+	return (ctx->reg_base_addr >> 9) & 0x7;
+}
+
+static void get_intlv_num_dies_df3(struct addr_ctx *ctx)
+{
+	ctx->intlv_num_dies  = (ctx->reg_base_addr >> 6) & 0x3;
+}
+
+static void get_intlv_num_sockets_df3(struct addr_ctx *ctx)
+{
+	ctx->intlv_num_sockets = (ctx->reg_base_addr >> 8) & 0x1;
+}
+
+static u8 get_die_id_shift_df3(struct addr_ctx *ctx)
+{
+	return ctx->node_id_shift;
+}
+
+static u8 get_socket_id_shift_df3(struct addr_ctx *ctx)
+{
+	return ((ctx->reg_fab_id_mask1 >> 8) & 0x3) + ctx->node_id_shift;
+}
+
+static int get_masks_df3(struct addr_ctx *ctx)
+{
+	if (amd_df_indirect_read(0, df_regs[SYS_FAB_ID_MASK_1],
+				 DF_BROADCAST, &ctx->reg_fab_id_mask1))
+		return -EINVAL;
+
+	ctx->node_id_shift = ctx->reg_fab_id_mask1 & 0xF;
+
+	ctx->die_id_mask = (ctx->reg_fab_id_mask1 >> 16) & 0x7;
+	ctx->die_id_mask <<= ctx->node_id_shift;
+
+	ctx->socket_id_mask = (ctx->reg_fab_id_mask1 >> 24) & 0x7;
+	ctx->socket_id_mask <<= ctx->node_id_shift;
+
+	return 0;
+}
+
+static u16 get_dst_fabric_id_df3(struct addr_ctx *ctx)
+{
+	return ctx->reg_limit_addr & 0x3FF;
+}
+
+static u16 get_component_id_mask_df3(struct addr_ctx *ctx)
+{
+	return ctx->reg_fab_id_mask0 & 0x3FF;
+}
+
+struct data_fabric_ops df3_ops = {
+	.get_hi_addr_offset		=	&get_hi_addr_offset_df3,
+	.get_intlv_mode			=	&get_intlv_mode_df3,
+	.get_intlv_addr_sel		=	&get_intlv_addr_sel_df3,
+	.get_intlv_num_dies		=	&get_intlv_num_dies_df3,
+	.get_intlv_num_sockets		=	&get_intlv_num_sockets_df3,
+	.get_cs_fabric_id		=	&get_cs_fabric_id_df2,
+	.get_masks			=	&get_masks_df3,
+	.get_die_id_shift		=	&get_die_id_shift_df3,
+	.get_socket_id_shift		=	&get_socket_id_shift_df3,
+	.get_dst_fabric_id		=	&get_dst_fabric_id_df3,
+	.get_component_id_mask		=	&get_component_id_mask_df3,
+};
+
 struct data_fabric_ops *df_ops;
 
 static int set_df_ops(struct addr_ctx *ctx)
@@ -1270,6 +1441,11 @@ static int set_df_ops(struct addr_ctx *ctx)
 				 DF_BROADCAST, &ctx->reg_fab_id_mask0))
 		return -EINVAL;
 
+	if ((ctx->reg_fab_id_mask0 & 0xFF) != 0) {
+		df_ops = &df3_ops;
+		return 0;
+	}
+
 	df_ops = &df2_ops;
 
 	return 0;
@@ -1332,8 +1508,8 @@ static int get_intlv_addr_bit(struct addr_ctx *ctx)
 {
 	u8 intlv_addr_sel = df_ops->get_intlv_addr_sel(ctx);
 
-	/* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
-	if (intlv_addr_sel > 3) {
+	/* {0, 1, 2, 3, 4} map to address bits {8, 9, 10, 11, 12} respectively */
+	if (intlv_addr_sel > 4) {
 		pr_debug("Invalid interleave address select %d.\n", intlv_addr_sel);
 		return -EINVAL;
 	}
@@ -1351,9 +1527,18 @@ static void get_intlv_num_chan(struct addr_ctx *ctx)
 		ctx->intlv_num_chan = 0;
 		break;
 	case NOHASH_2CH:
+	case HASH_COD4_2CH:
 	case DF2_HASH_2CH:
 		ctx->intlv_num_chan = 1;
 		break;
+	case NOHASH_4CH:
+	case HASH_COD2_4CH:
+		ctx->intlv_num_chan = 2;
+		break;
+	case NOHASH_8CH:
+	case HASH_COD1_8CH:
+		ctx->intlv_num_chan = 3;
+		break;
 	default:
 		/* Valid interleaving modes where checked earlier. */
 		break;
-- 
2.25.1


  parent reply	other threads:[~2021-06-23 19:23 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-23 19:19 [PATCH v2 00/31] AMD MCA Address Translation Updates Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 01/31] x86/MCE/AMD, EDAC/amd64: Move address translation to AMD64 EDAC Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 02/31] x86/amd_nb, EDAC/amd64: Move DF Indirect Read " Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 03/31] EDAC/amd64: Don't use naked values for DF registers Yazen Ghannam
2021-06-25 15:21   ` Borislav Petkov
2021-07-08 19:35     ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 04/31] EDAC/amd64: Allow for DF Indirect Broadcast reads Yazen Ghannam
2021-06-30 16:22   ` Borislav Petkov
2021-07-08 19:44     ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 05/31] EDAC/amd64: Add context struct Yazen Ghannam
2021-06-30 17:17   ` Borislav Petkov
2021-07-08 19:53     ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 06/31] EDAC/amd64: Define Data Fabric operations Yazen Ghannam
2021-06-30 17:19   ` Borislav Petkov
2021-07-08 19:55     ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 07/31] EDAC/amd64: Define functions for DramOffset Yazen Ghannam
2021-06-30 17:27   ` Borislav Petkov
2021-07-08 20:08     ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 08/31] EDAC/amd64: Define function to read DRAM address map registers Yazen Ghannam
2021-06-30 17:29   ` Borislav Petkov
2021-06-23 19:19 ` [PATCH v2 09/31] EDAC/amd64: Define function to find interleaving mode Yazen Ghannam
2021-06-30 17:33   ` Borislav Petkov
2021-07-08 20:09     ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 10/31] EDAC/amd64: Define function to denormalize address Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 11/31] EDAC/amd64: Define function to add DRAM base and hole Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 12/31] EDAC/amd64: Define function to dehash address Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 13/31] EDAC/amd64: Define function to check DRAM limit address Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 14/31] EDAC/amd64: Remove goto statements Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 15/31] EDAC/amd64: Simplify function parameters Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 16/31] EDAC/amd64: Define function to get Interleave Address Bit Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 17/31] EDAC/amd64: Skip denormalization if no interleaving Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 18/31] EDAC/amd64: Define function to get number of interleaved channels Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 19/31] EDAC/amd64: Define function to get number of interleaved dies Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 20/31] EDAC/amd64: Define function to get number of interleaved sockets Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 21/31] EDAC/amd64: Remove unnecessary assert Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 22/31] EDAC/amd64: Define function to make space for CS ID Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 23/31] EDAC/amd64: Define function to calculate " Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 24/31] EDAC/amd64: Define function to insert CS ID into address Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 25/31] EDAC/amd64: Define function to get CS Fabric ID Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 26/31] EDAC/amd64: Define function to find shift and mask values Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 27/31] EDAC/amd64: Update CS ID calculation to match reference code Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 28/31] EDAC/amd64: Match hash function to " Yazen Ghannam
2021-06-23 19:20 ` [PATCH v2 29/31] EDAC/amd64: Define helper function to get interleave address select bit Yazen Ghannam
2021-06-23 19:20 ` Yazen Ghannam [this message]
2021-06-23 19:20 ` [PATCH v2 31/31] EDAC/amd64: Add glossary of acronyms for address translation Yazen Ghannam

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