Re: [PATCH 2/2] x86/mce: Add support for Extended Physical Address MCA changes

[Yazen Ghannam <yazen.ghannam@amd.com>]

On Thu, Jun 24, 2021 at 08:33:41PM -0500, Smita Koralahalli wrote:
> Newer AMD processors such as AMD 'Milan' support more physical address
> bits.
> 
> That is the MCA_ADDR registers on Scalable MCA systems contain the
> ErrorAddr in bits [56:0] instead of [55:0]. Hence the existing LSB field
> from bits [61:56] in MCA_ADDR must be moved around to accommodate the
> larger ErrorAddr size.
> 
> MCA_CONFIG[McaLsbInStatusSupported] indicates this change. If set, the
> LSB field will be found in MCA_STATUS rather than MCA_ADDR.
> 
> Each logical CPU has unique MCA bank in hardware and is not shared with
> other logical CPUs. Additionally on SMCA systems, each feature bit may be
> different for each bank within same logical CPU.
> 
> Check for MCA_CONFIG[McaLsbInStatusSupported] for each MCA bank and for
> each CPU.
> 
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
> ---

Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Tested-by: Yazen Ghannam <yazen.ghannam@amd.com>

Thanks,
Yazen

P.S. A good test case for this feature is data poison consumption on
Milan. This case will generate two MCA errors. One will be a deferred
error in the UMC bank. This will be handled through the deferred error
interrupt handler. Also, the UMC bank does not have the "LSB in Status"
feature. The other error will be a #MC in the Load Store bank. This
bank does have the "LSB in Status" feature.