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From: Zong Li <zong.li@sifive.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	aou@eecs.berkeley.edu, greentime.hu@sifive.com,
	conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v5 6/7] soc: sifive: ccache: define the macro for the register shifts
Date: Tue, 13 Sep 2022 06:18:16 +0000	[thread overview]
Message-ID: <20220913061817.22564-7-zong.li@sifive.com> (raw)
In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com>

Define the macro for the register shifts, it could make the code be
more readable

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/soc/sifive/sifive_ccache.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 91f0c2b32ea2..1c171150e878 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -13,6 +13,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <linux/device.h>
+#include <linux/bitfield.h>
 #include <asm/cacheinfo.h>
 #include <soc/sifive/sifive_ccache.h>
 
@@ -33,6 +34,11 @@
 #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
 
 #define SIFIVE_CCACHE_CONFIG 0x00
+#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)
+#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)
+#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
+#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
+
 #define SIFIVE_CCACHE_WAYENABLE 0x08
 #define SIFIVE_CCACHE_ECCINJECTERR 0x40
 
@@ -87,11 +93,11 @@ static void ccache_config_read(void)
 	u32 cfg;
 
 	cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
-
-	pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
-		(cfg & 0xff), (cfg >> 8) & 0xff,
-		BIT_ULL((cfg >> 16) & 0xff),
-		BIT_ULL((cfg >> 24) & 0xff));
+	pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n",
+		FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg),
+		FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg),
+		BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),
+		BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));
 
 	cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
 	pr_info("Index of the largest way enabled: %u\n", cfg);
-- 
2.17.1


  parent reply	other threads:[~2022-09-13  6:19 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13  6:18 [PATCH v5 0/7] Use composable cache instead of L2 cache Zong Li
2022-09-13  6:18 ` [PATCH v5 1/7] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Zong Li
2022-09-13  6:18 ` [PATCH v5 2/7] soc: sifive: ccache: Rename SiFive " Zong Li
2022-09-13  6:18 ` [PATCH v5 3/7] soc: sifive: ccache: determine the cache level from dts Zong Li
2022-09-13  6:18 ` [PATCH v5 4/7] soc: sifive: ccache: reduce printing on init Zong Li
2022-09-13  6:18 ` [PATCH v5 5/7] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Zong Li
2022-09-13  6:18 ` Zong Li [this message]
2022-09-13  6:18 ` [PATCH v5 7/7] riscv: Add cache information in AUX vector Zong Li
2022-09-13 10:34   ` Conor.Dooley
2022-09-21  5:09 ` [PATCH v5 0/7] Use composable cache instead of L2 cache Zong Li
2022-10-03  2:42   ` Zong Li
2022-10-04 14:20   ` Ben Dooks
2022-10-13 19:45 ` Palmer Dabbelt

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