From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, bp@alien8.de,
tony.luck@intel.com
Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
james.morse@arm.com, mchehab@kernel.org, rric@kernel.org,
linux-edac@vger.kernel.org, quic_ppareek@quicinc.com,
luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v5 06/17] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks
Date: Wed, 28 Dec 2022 14:10:17 +0530 [thread overview]
Message-ID: <20221228084028.46528-7-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org>
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as
there are LLCC BWMON registers located after this range.
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 65032b94b46d..4db68d4d78df 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2132,8 +2132,11 @@ uart15: serial@a9c000 {
llcc: system-cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
- reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
+ reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
+ <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
+ <0 0x01300000 0 0x50000>;
+ reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
+ "llcc3_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.25.1
next prev parent reply other threads:[~2022-12-28 8:42 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-28 8:40 [PATCH v5 00/17] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 01/17] EDAC/device: Make use of poll_msec value in edac_device_ctl_info struct Manivannan Sadhasivam
2022-12-28 11:17 ` Borislav Petkov
2022-12-28 8:40 ` [PATCH v5 02/17] EDAC/qcom: Add platform_device_id table for module autoloading Manivannan Sadhasivam
2022-12-28 11:54 ` Borislav Petkov
2022-12-28 8:40 ` [PATCH v5 03/17] EDAC/qcom: Do not pass llcc_driv_data as edac_device_ctl_info's pvt_info Manivannan Sadhasivam
2022-12-28 11:58 ` Borislav Petkov
2022-12-28 8:40 ` [PATCH v5 04/17] dt-bindings: arm: msm: Update the maintainers for LLCC Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 05/17] dt-bindings: arm: msm: Fix register regions used for LLCC banks Manivannan Sadhasivam
2022-12-28 8:40 ` Manivannan Sadhasivam [this message]
2022-12-28 8:40 ` [PATCH v5 07/17] arm64: dts: qcom: sc7180: Fix the base addresses of " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 08/17] arm64: dts: qcom: sc7280: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 09/17] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 10/17] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 11/17] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 12/17] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 13/17] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 14/17] arm64: dts: qcom: sm6350: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 15/17] qcom: llcc/edac: Fix the base address used for accessing " Manivannan Sadhasivam
2023-01-14 13:27 ` Borislav Petkov
2023-01-15 4:01 ` Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 16/17] qcom: llcc/edac: Support polling mode for ECC handling Manivannan Sadhasivam
2023-01-14 13:36 ` Borislav Petkov
2023-01-15 4:08 ` Manivannan Sadhasivam
2023-01-16 10:41 ` Borislav Petkov
2023-01-18 15:08 ` Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 17/17] soc: qcom: llcc: Do not create EDAC platform device on SDM845 Manivannan Sadhasivam
2022-12-28 10:36 ` [PATCH v5 00/17] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Borislav Petkov
2022-12-28 16:47 ` Manivannan Sadhasivam
2022-12-28 17:55 ` Borislav Petkov
2023-01-02 17:30 ` Manivannan Sadhasivam
2023-01-14 7:12 ` Manivannan Sadhasivam
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