From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D632EC6FD1C for ; Tue, 14 Mar 2023 08:05:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230410AbjCNIFM (ORCPT ); Tue, 14 Mar 2023 04:05:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230390AbjCNIFJ (ORCPT ); Tue, 14 Mar 2023 04:05:09 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7468867701 for ; Tue, 14 Mar 2023 01:05:05 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id ja10so6046535plb.5 for ; Tue, 14 Mar 2023 01:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781105; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E3ynFMYwQcpfXg1vBUZGiwqSjOZbWEHjnhI8PWp4GCE=; b=j7xvaNy2aA+o+3gb3Dvuc5Gw42SQp4fw7wM3jyYBLIU+W2YQWfLA3pC7l/N1UA8/BE BkoZsjVK32Wfus2lsJfzYjm550ld0xIFD5JvEEcEDbuMspSarOq54iEz0WTn59NegK0J RM6T4zNBgRYgRi75maX+ZIr5qv3tGSDQcGRQs1nv8c2LMDPmOerqVbACYaP8dWQ5CpbT WPToLBnPAf+emWdkUaXPDOeVxPYlBq9I7dvStU2ZdaiMUmMbinG414mp9y/duh7F0FI0 Ac055n7DGUye+GOoEk5pNTt8tM5m0Ej88zqCpoWtaZt4Mw6Fer45C8j1XmBaocofZNgz ITBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781105; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E3ynFMYwQcpfXg1vBUZGiwqSjOZbWEHjnhI8PWp4GCE=; b=hKQDGVz2wAkbt7i18+KRGWjD8jquc00omJIoydj6/08r0egYv88qGNf26Vu+r9GFNw Ukuzb/XOa1WQN5mp3c/W17Vlb4Og5XyqRROCEiNZ2YeP+cmZCM5cDdvCgwMafu90jvSh VAjq0uD/mYPj84AwWsikXNUvjFJ/167Z7rA1SsneqeMMRSDQ6RjpIpv1Weai81IF1XaU Pu+5rq7LInw3wHBMozIqkZ9HJfvvsFczPJNKDKHAknVB0ME11ayZ+aNo6BdhwGwgzOTs eYtEwxYRH34+1v2tQZAARQS5VRndUymSBzQYK3W1GEszyd9ZX/ZlxZFfb1a55pQQdgXo 81hQ== X-Gm-Message-State: AO0yUKUTSp9f4rhBGZPHfIHPBNkIjspsgqeDrN55LPXZfELgTmk5LCwM vfU55D1hXdi7ZbAf9fa0E5Js X-Google-Smtp-Source: AK7set+dn8942e/cqeFhAuAmJLdev5Ni6BMCm2yi8gCsc2582luPHUX9sBl743YZQEgf2T+6vQLv3w== X-Received: by 2002:a17:902:c949:b0:19e:416e:abf5 with SMTP id i9-20020a170902c94900b0019e416eabf5mr13643147pla.34.1678781104771; Tue, 14 Mar 2023 01:05:04 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:03 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v8 02/14] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Tue, 14 Mar 2023 13:34:31 +0530 Message-Id: <20230314080443.64635-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 6570b808fd0d..93b977428a14 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = ; + }; }; -- 2.25.1