From: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
To: "tony.luck@intel.com" <tony.luck@intel.com>,
"Borislav Petkov (bp@alien8.de)" <bp@alien8.de>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"x86@kernel.org" <x86@kernel.org>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"yazen.ghannam@amd.com" <yazen.ghannam@amd.com>,
"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
"qiuxu.zhuo@intel.com" <qiuxu.zhuo@intel.com>
Cc: David Wang <DavidWang@zhaoxin.com>,
"Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>,
"Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>,
"Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Subject: [PATCH v1 3/4] x86/mce: Add Zhaoxin CMCI support
Date: Mon, 9 Sep 2019 10:21:22 +0000 [thread overview]
Message-ID: <29e895912c2f4989937fa33d59e55dd9@zhaoxin.com> (raw)
All Zhaoxin newer CPUs support CMCI that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin CMCI in
mce/core.c and mce/intel.c.
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
---
arch/x86/include/asm/mce.h | 6 ++++++
arch/x86/kernel/cpu/mce/core.c | 25 +++++++++++++++++++++++++
arch/x86/kernel/cpu/mce/intel.c | 3 ++-
3 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index dc2d4b2..0986a11 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -350,4 +350,10 @@ umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return
static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
+#ifdef CONFIG_CPU_SUP_ZHAOXIN
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c);
+#else
+static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
+#endif
+
#endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 3f878f6..a3b07ca 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1777,6 +1777,27 @@ static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
}
}
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+ * These CPUs bank8 SVAD error may be triggered unexpected when
+ * bringup virtual machine. it is not hardware bug. Always disable
+ * bank8 SVAD error by default.
+ */
+ if ((c->x86 == 6 && c->x86_model == 0x19 &&
+ (c->x86_stepping > 3 && c->x86_stepping < 8)) ||
+ (c->x86 == 6 && c->x86_model == 0x1f) ||
+ (c->x86 == 7 && c->x86_model == 0x1b)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ intel_init_cmci();
+ mce_adjust_timer = cmci_intel_adjust_timer;
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1798,6 +1819,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
mce_centaur_feature_init(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_init(c);
+ break;
+
default:
break;
}
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index eee4b12..b49cba7 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -85,7 +85,8 @@ static int cmci_supported(int *banks)
* initialization is vendor keyed and this
* makes sure none of the backdoors are entered otherwise.
*/
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 0;
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return 0;
--
2.7.4
next reply other threads:[~2019-09-09 10:36 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-09 10:21 Tony W Wang-oc [this message]
2019-09-09 14:47 ` [PATCH v1 3/4] x86/mce: Add Zhaoxin CMCI support kbuild test robot
2019-09-10 8:17 ` 答复: " Tony W Wang-oc
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