答复: [PATCH v2 1/4] x86/mce: Add Zhaoxin MCE support - Tony W Wang-oc

From: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
To: Borislav Petkov <bp@alien8.de>
Cc: "tony.luck@intel.com" <tony.luck@intel.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"yazen.ghannam@amd.com" <yazen.ghannam@amd.com>,
	"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
	"qiuxu.zhuo@intel.com" <qiuxu.zhuo@intel.com>,
	David Wang <DavidWang@zhaoxin.com>,
	"Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>,
	"Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>,
	"Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Subject: 答复: [PATCH v2 1/4] x86/mce: Add Zhaoxin MCE support
Date: Wed, 11 Sep 2019 10:10:48 +0000	[thread overview]
Message-ID: <3ebc05282ec948288af9e6060e5a474e@zhaoxin.com> (raw)
In-Reply-To: <20190910115116.GD23931@zn.tnic>

On Tue, Sep 10, 2019, Borislav Petkov wrote:
>On Tue, Sep 10, 2019 at 08:19:08AM +0000, Tony W Wang-oc wrote:
>> All Zhaoxin newer CPUs support MCE that compatible with Intel's
>> "Machine-Check Architecture", so add support for Zhaoxin MCE in
>> mce/core.c.
>>
>> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
>> ---
>>  arch/x86/kernel/cpu/mce/core.c | 30 ++++++++++++++++++++++++------
>>  1 file changed, 24 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
>> index 743370e..3f878f6 100644
>> --- a/arch/x86/kernel/cpu/mce/core.c
>> +++ b/arch/x86/kernel/cpu/mce/core.c
>> @@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)
>>  	if (!(m->status & MCI_STATUS_ADDRV))
>>  		return 0;
>>
>> -	/* Checks after this one are Intel-specific: */
>> -	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
>> +	/* Checks after this one are Intel/Zhaoxin-specific: */
>> +	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
>> +	    boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
>>  		return 1;
>>
>>  	if (!(m->status & MCI_STATUS_MISCV))
>> @@ -510,7 +511,8 @@ bool mce_is_memory_error(struct mce *m)
>>  	if (m->cpuvendor == X86_VENDOR_AMD ||
>>  	    m->cpuvendor == X86_VENDOR_HYGON) {
>>  		return amd_mce_is_memory_error(m);
>> -	} else if (m->cpuvendor == X86_VENDOR_INTEL) {
>> +	} else if (m->cpuvendor == X86_VENDOR_INTEL ||
>> +		   m->cpuvendor == X86_VENDOR_ZHAOXIN) {
>>  		/*
>>  		 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
>>  		 *
>
>Make that a switch-case for better readability pls.

Ok.

>
>> @@ -1697,6 +1699,21 @@ static int __mcheck_cpu_apply_quirks(struct
>cpuinfo_x86 *c)
>>  		if (c->x86 == 6 && c->x86_model == 45)
>>  			quirk_no_way_out = quirk_sandybridge_ifu;
>>  	}
>> +
>> +	if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
>> +		/*
>> +		 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
>> +		 * synchronization with a one second timeout.
>> +		 */
>> +		if ((c->x86 == 6 && c->x86_model == 0x19 &&
>> +			(c->x86_stepping > 3 && c->x86_stepping < 8)) ||
>> +		    (c->x86 == 6 && c->x86_model == 0x1f) ||
>> +		     c->x86 > 6) {
>
>Can this be simplified into maybe something like this:
>
>	if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f))
>
>this is, of course, assuming that Zhaoxin doesn't do family < 6 and that
>the other steppings for model 0x19 don't matter because they don't exist
>or so...
>

Yes, Zhaoxin doesn't do family<6, and the other steppings for model 0x19
doesn't have MCA. So will simplified like this:
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f))

Sincerely
TonyWWang-oc