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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u25-20020ac258d9000000b004a26ba3458fsm221776lfo.62.2022.10.05.07.59.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Oct 2022 07:59:53 -0700 (PDT) Message-ID: <3ee1bff2-ab11-2dcd-aede-628d2735d6de@linaro.org> Date: Wed, 5 Oct 2022 16:59:52 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Content-Language: en-US To: Rob Herring , Serge Semin Cc: Dinh Nguyen , Michail Ivanov , James Morse , Michal Simek , Tony Luck , Punnaiah Choudary Kalluri , linux-edac@vger.kernel.org, Borislav Petkov , Serge Semin , Robert Richter , Alexey Malahov , linux-arm-kernel@lists.infradead.org, Pavel Parkhomenko , linux-kernel@vger.kernel.org, Mauro Carvalho Chehab , Manish Narani , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org References: <20220929234121.13955-1-Sergey.Semin@baikalelectronics.ru> <20220929234121.13955-3-Sergey.Semin@baikalelectronics.ru> <166479586876.1658787.6925988592765037866.robh@kernel.org> From: Krzysztof Kozlowski In-Reply-To: <166479586876.1658787.6925988592765037866.robh@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On 03/10/2022 15:24, Rob Herring wrote: > On Fri, 30 Sep 2022 02:41:10 +0300, Serge Semin wrote: >> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a >> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There >> are individual IRQs for each ECC and DFI events. The dedicated scrubber >> clock source is absent since it's fully synchronous to the core clock. >> In addition to that the DFI-DDR PHY CSRs can be accessed via a separate >> registers space. >> >> Signed-off-by: Serge Semin >> Reviewed-by: Rob Herring >> >> --- >> >> Changelog v2: >> - Keep the alphabetically ordered compatible strings list. (@Krzysztof) >> - Fix grammar nitpicks in the patch log. (@Krzysztof) >> - Drop the PHY CSR region. (@Rob) >> - Move the device bindings to the separate DT-schema. >> --- >> .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ >> 1 file changed, 91 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > ./Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml This is result of patch #1 failing to apply: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20220929234121.13955-2-Sergey.Semin@baikalelectronics.ru/ The bindings look ok, but anyway it is a merge window now. Best regards, Krzysztof