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* Re: [PATCH 0/2] Add EDAC support for Kryo CPU core caches
       [not found] <0101016ed57a10a8-bd8fbdb9-a5cd-4460-bae6-c5c35f0eed88-000000@us-west-2.amazonses.com>
@ 2020-01-15 18:46 ` James Morse
  2020-01-24 14:04   ` Sai Prakash Ranjan
  0 siblings, 1 reply; 3+ messages in thread
From: James Morse @ 2020-01-15 18:46 UTC (permalink / raw)
  To: Sai Prakash Ranjan
  Cc: Andy Gross, Bjorn Andersson, Mark Rutland, Rob Herring,
	devicetree, Borislav Petkov, Mauro Carvalho Chehab, Tony Luck,
	Robert Richter, linux-edac, tsoni, linux-arm-msm, linux-kernel,
	Evan Green, Stephen Boyd, psodagud, linux-arm-kernel, baicar

Hi Sai,

(CC: +Tyler)

On 05/12/2019 09:52, Sai Prakash Ranjan wrote:
> This series implements EDAC support for error reporting on
> Kryo{3,4}XX CPU caches L1,L2, L3-SCU. All the cores(big.LITTLE)
> in Kryo{3,4}XX CPUs implement RAS extensions and use interrupt
> based ECC mechanism to report errors.
> 
> This series has been tested on SC7180, SDM845, SM8150 SoCs with
> Kryo{3,4}XX CPU cores based on ARM Cortex-A55, Cortex-A75 and
> Cortex-A76.
> 
> This implementation is platform specific in contrast to the
> patch posted last time for generic error reporting on arm cortex
> implementations with RAS extensions by Kyle Yan.
>  - https://patchwork.kernel.org/patch/10161955/

I think that series was dropped because it was too soc-specific and overlaps with the v8.2
kernel first support. That series was superseded by:
lore.kernel.org/r/1562086280-5351-1-git-send-email-baicar@os.amperecomputing.com

Can you work with Tyler on a combined series? The combined support may need to look quite
different. (DT and big/little being the obvious differences).

I'm afraid this is the tip of the kernel-first-RAS iceberg.


Thanks,

James

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH 0/2] Add EDAC support for Kryo CPU core caches
  2020-01-15 18:46 ` [PATCH 0/2] Add EDAC support for Kryo CPU core caches James Morse
@ 2020-01-24 14:04   ` Sai Prakash Ranjan
  0 siblings, 0 replies; 3+ messages in thread
From: Sai Prakash Ranjan @ 2020-01-24 14:04 UTC (permalink / raw)
  To: James Morse
  Cc: Andy Gross, Bjorn Andersson, Mark Rutland, Rob Herring,
	devicetree, Borislav Petkov, Mauro Carvalho Chehab, Tony Luck,
	Robert Richter, linux-edac, tsoni, linux-arm-msm, linux-kernel,
	Evan Green, Stephen Boyd, psodagud, linux-arm-kernel, baicar

Hello James,

On 2020-01-16 00:16, James Morse wrote:
> Hi Sai,
> 
> (CC: +Tyler)
> 
> On 05/12/2019 09:52, Sai Prakash Ranjan wrote:
>> This series implements EDAC support for error reporting on
>> Kryo{3,4}XX CPU caches L1,L2, L3-SCU. All the cores(big.LITTLE)
>> in Kryo{3,4}XX CPUs implement RAS extensions and use interrupt
>> based ECC mechanism to report errors.
>> 
>> This series has been tested on SC7180, SDM845, SM8150 SoCs with
>> Kryo{3,4}XX CPU cores based on ARM Cortex-A55, Cortex-A75 and
>> Cortex-A76.
>> 
>> This implementation is platform specific in contrast to the
>> patch posted last time for generic error reporting on arm cortex
>> implementations with RAS extensions by Kyle Yan.
>>  - https://patchwork.kernel.org/patch/10161955/
> 
> I think that series was dropped because it was too soc-specific and
> overlaps with the v8.2
> kernel first support. That series was superseded by:
> lore.kernel.org/r/1562086280-5351-1-git-send-email-baicar@os.amperecomputing.com
> 
> Can you work with Tyler on a combined series? The combined support may
> need to look quite
> different. (DT and big/little being the obvious differences).
> 
> I'm afraid this is the tip of the kernel-first-RAS iceberg.
> 

Sorry for the delayed response. Sure, I will take a look at the series 
posted by Tyler.
It might take some time to come up with that but should be doable with 
your review :)

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH 0/2] Add EDAC support for Kryo CPU core caches
@ 2019-12-05  9:52 Sai Prakash Ranjan
  0 siblings, 0 replies; 3+ messages in thread
From: Sai Prakash Ranjan @ 2019-12-05  9:52 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Mark Rutland, Rob Herring,
	devicetree, Borislav Petkov, Mauro Carvalho Chehab, Tony Luck,
	James Morse, Robert Richter, linux-edac
  Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, Stephen Boyd,
	Evan Green, tsoni, psodagud, Sai Prakash Ranjan

This series implements EDAC support for error reporting on
Kryo{3,4}XX CPU caches L1,L2, L3-SCU. All the cores(big.LITTLE)
in Kryo{3,4}XX CPUs implement RAS extensions and use interrupt
based ECC mechanism to report errors.

This series has been tested on SC7180, SDM845, SM8150 SoCs with
Kryo{3,4}XX CPU cores based on ARM Cortex-A55, Cortex-A75 and
Cortex-A76.

This implementation is platform specific in contrast to the
patch posted last time for generic error reporting on arm cortex
implementations with RAS extensions by Kyle Yan.
 - https://patchwork.kernel.org/patch/10161955/

Downstream implementation of this can be found at:
 - https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/drivers/edac/kryo_arm64_edac.c?h=msm-4.14

Sai Prakash Ranjan (2):
  dt-bindings: edac: Add DT bindings for Kryo EDAC
  drivers: edac: Add EDAC support for Kryo CPU caches

 .../bindings/edac/qcom-kryo-edac.yaml         |  67 ++
 MAINTAINERS                                   |   7 +
 drivers/edac/Kconfig                          |  20 +
 drivers/edac/Makefile                         |   1 +
 drivers/edac/qcom_kryo_edac.c                 | 679 ++++++++++++++++++
 5 files changed, 774 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml
 create mode 100644 drivers/edac/qcom_kryo_edac.c

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 3+ messages in thread

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2020-01-15 18:46 ` [PATCH 0/2] Add EDAC support for Kryo CPU core caches James Morse
2020-01-24 14:04   ` Sai Prakash Ranjan
2019-12-05  9:52 Sai Prakash Ranjan

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