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From: Thor Thayer <thor.thayer@linux.intel.com>
To: bp@alien8.de, mchehab@kernel.org, james.morse@arm.com,
	robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org
Cc: devicetree@vger.kernel.org, linux-edac@vger.kernel.org
Subject: Re: [PATCH 1/3] Documentation: dt: edac: Add reg to S10 SDRAM node
Date: Fri, 12 Jul 2019 10:27:37 -0500
Message-ID: <803a63f8-c096-f1ec-7a80-c54d6c1f6281@linux.intel.com> (raw)
In-Reply-To: <1562711090-900-2-git-send-email-thor.thayer@linux.intel.com>

On 7/9/19 5:24 PM, thor.thayer@linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
> 
> Include the register offset and size in the Stratix10 SDRAM node
> to be consistent with other ECC modules.
> Previously had to follow the phandle to get the register size/offset.
> 
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> ---
>   Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
> index 8f52206cfd2a..dd6ba6c020a7 100644
> --- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
> +++ b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
> @@ -256,6 +256,7 @@ Subcomponents:
>   SDRAM ECC
>   Required Properties:
>   - compatible : Should be "altr,sdram-edac-s10"
> +- reg        : Address and size for ECC block registers.
>   - interrupts : Should be single bit error interrupt.
>   
>   On-Chip RAM ECC
> @@ -313,8 +314,9 @@ Example:
>   		#interrupt-cells = <2>;
>   		ranges;
>   
> -		sdramedac {
> +		sdramedac@0xf8011100 {
>   			compatible = "altr,sdram-edac-s10";
> +			reg = <0xf8011100 0xc0>;
>   			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
>   		};
>   
> 
Please disregard this patch, there is a simpler solution that I will 
submit shortly.

  reply index

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-09 22:24 [PATCH 0/3] Stratix10 SDRAM Common EDAC Framework thor.thayer
2019-07-09 22:24 ` [PATCH 1/3] Documentation: dt: edac: Add reg to S10 SDRAM node thor.thayer
2019-07-12 15:27   ` Thor Thayer [this message]
2019-07-09 22:24 ` [PATCH 2/3] arm64: dts: Stratix10: Include regs in SDRAM ECC node thor.thayer
2019-07-12 15:27   ` Thor Thayer
2019-07-09 22:24 ` [PATCH 3/3] EDAC, altera: Use common framework for Stratix10 SDRAM ECC thor.thayer
2019-07-12 15:26 ` [PATCH 0/3] Stratix10 SDRAM Common EDAC Framework Thor Thayer

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