From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E12BC43461 for ; Thu, 1 Apr 2021 18:11:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 044BC60FE6 for ; Thu, 1 Apr 2021 18:11:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236587AbhDASLN (ORCPT ); Thu, 1 Apr 2021 14:11:13 -0400 Received: from mail.kernel.org ([198.145.29.99]:37004 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236809AbhDASDB (ORCPT ); Thu, 1 Apr 2021 14:03:01 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4F74461355; Thu, 1 Apr 2021 15:37:09 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lRzNb-0057PC-4y; Thu, 01 Apr 2021 16:37:07 +0100 Date: Thu, 01 Apr 2021 16:37:06 +0100 Message-ID: <87pmzeow2l.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Hauer Cc: linux-edac@vger.kernel.org, Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , James Morse , Robert Richter , York Sun , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org, Rob Herring , Mark Rutland Subject: Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property In-Reply-To: <20210401110615.15326-3-s.hauer@pengutronix.de> References: <20210401110615.15326-1-s.hauer@pengutronix.de> <20210401110615.15326-3-s.hauer@pengutronix.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: s.hauer@pengutronix.de, linux-edac@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, james.morse@arm.com, rrichter@marvell.com, york.sun@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, mark.rutland@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On Thu, 01 Apr 2021 12:06:15 +0100, Sascha Hauer wrote: > > Some CPUs like the Cortex-A53 and Cortex-A57 have Error Detection And > Correction (EDAC) support on their L1 and L2 caches. This is implemented > in implementation defined registers, so usage of this functionality is > not safe in virtualized environments or when EL3 already uses these > registers. > This patch adds a edac-enabled flag which can be explicitly set when > EDAC can be used. > > Signed-off-by: Sascha Hauer > --- > Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++ > drivers/edac/cortex_arm64_l1_l2.c | 7 +++++-- > 2 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml > index 26b886b20b27..74be19c0544a 100644 > --- a/Documentation/devicetree/bindings/arm/cpus.yaml > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml > @@ -270,6 +270,12 @@ properties: > For PSCI based platforms, the name corresponding to the index of the PSCI > PM domain provider, must be "psci". > > + edac-enabled: > + $ref: '/schemas/types.yaml#/definitions/flag' > + description: > + Some CPUs support Error Detection And Correction (EDAC) on their L1 and > + L2 caches. This flag marks this function as usable. > + > qcom,saw: > $ref: '/schemas/types.yaml#/definitions/phandle' > description: | > diff --git a/drivers/edac/cortex_arm64_l1_l2.c b/drivers/edac/cortex_arm64_l1_l2.c > index 3b1e2f3ccab6..6d5355bae80c 100644 > --- a/drivers/edac/cortex_arm64_l1_l2.c > +++ b/drivers/edac/cortex_arm64_l1_l2.c > @@ -190,8 +190,11 @@ static int __init cortex_arm64_edac_driver_init(void) > for_each_possible_cpu(cpu) { > np = of_get_cpu_node(cpu, NULL); > > - if (of_match_node(cortex_arm64_edac_of_match, np)) > - cpumask_set_cpu(cpu, &compat_mask); > + if (!of_match_node(cortex_arm64_edac_of_match, np)) > + continue; > + if (!of_property_read_bool(np, "edac-enabled")) > + continue; > + cpumask_set_cpu(cpu, &compat_mask); > } > > if (cpumask_empty(&compat_mask)) This last hunk must be part of the initial patch. Otherwise, it breaks exactly as described in the commit message. Thanks, M. -- Without deviation from the norm, progress is not possible.