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([2001:b07:6468:f312:e876:e214:dc8e:2846]) by smtp.gmail.com with ESMTPSA id a14sm1603922wmm.44.2019.10.07.23.55.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Oct 2019 23:55:47 -0700 (PDT) Subject: Re: [PATCH 10/16] x86/cpu: Detect VMX features on Intel, Centaur and Zhaoxin CPUs To: Sean Christopherson Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, Peter Zijlstra , Arnaldo Carvalho de Melo , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Tony Luck , Tony W Wang-oc , "H. Peter Anvin" , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-edac@vger.kernel.org, Borislav Petkov , Jarkko Sakkinen References: <20191004215615.5479-1-sean.j.christopherson@intel.com> <20191004215615.5479-11-sean.j.christopherson@intel.com> <20191007195422.GF18016@linux.intel.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: <8b44345d-7bc0-b8f2-0ee4-3e7f3c8bd994@redhat.com> Date: Tue, 8 Oct 2019 08:55:50 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20191007195422.GF18016@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On 07/10/19 21:54, Sean Christopherson wrote: >> For QEMU, we're defining a feature as supported if a feature can be >> turned both on and off. Since msr_low and msr_high can be defined >> respectively as must-be-one and can-be-one, the features become >> "msr_high & ~msr_low". > > That makes sense for Qemu, but I don't think it's appropriate for this > type of reporting. E.g. if EPT and Unrestricted Guest are must-be-one on > a hypothetical (virtual) CPU, it'd be odd to not list them as a supported > feature. > > For actual hardware (well, Intel hardware), as proposed it's a moot point. > The only features that are must-be-one (even without "true" MSRs) and are > documented in the SDM are CR3_LOAD_EXITING, CR3_STORE_EXITING, > SAVE_DEBUG_CONTROLS, and LOAD_DEBUG_CONTROLS, none of which are reported > in /proc/cpuinfo. > >> Also, shouldn't this use the "true" feature availability MSRs if available? > > Only if incorporating the "& ~msr_low" can-be-one logic. If a feature is > considered supported if it must-be-one or can-be-one then the true MSR and > vanilla MSR will yield the same feature set. Ok, that all makes sense. Paolo