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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL1PR12MB5286.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3a068562-919e-42a2-fe21-08d95bfcb6ea X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Aug 2021 12:45:20.7310 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: f6gRFSv7U+zhp9hZbE13dW/2hBydxH2jxCpkvz5AoaorSe/vXPlBQ06FPfI932phEh0rTfdx1wdOs6pU9dxmYQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5335 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org [Public] Hi Yazen Regards, Naveenk -----Original Message----- From: Ghannam, Yazen =20 Sent: Tuesday, July 20, 2021 1:56 AM To: Chatradhi, Naveen Krishna Cc: linux-edac@vger.kernel.org; x86@kernel.org; linux-kernel@vger.kernel.or= g; bp@alien8.de; mingo@redhat.com; mchehab@kernel.org Subject: Re: [PATCH 2/7] x86/amd_nb: Add support for northbridges on Aldeba= ran On Wed, Jun 30, 2021 at 08:58:23PM +0530, Naveen Krishna Chatradhi wrote: > From: Muralidhara M K >=20 > On newer heterogeneous systems from AMD, there is a possibility of=20 > having GPU nodes along with CPU nodes with the MCA banks. The GPU=20 > nodes (noncpu nodes) starts enumerating from northbridge index 8. > "there is a possibility of having GPU nodes along with CPU nodes with the M= CA banks" doesn't read clearly to me. It could be more explicit. For example, "On newer systems...the CPUs manages MCA errors reported from = the GPUs. Enumerate the GPU nodes with the AMD NB framework to support EDAC= , etc." or something like this. Also, "northbridge index" isn't a hardware thing rather it's an internal Li= nux value. I think you are referring to the "AMD Node ID" value from CPUID.= The GPUs don't have CPUID, so the "AMD Node ID" value can't be directly re= ad like for CPUs. But the current hardware implementation is such that the = GPU nodes are enumerated in sequential order based on the PCI hierarchy, an= d the first GPU node is assumed to have an "AMD Node ID" value of 8 (the se= cond GPU node has 9, etc.). With this implemenation detail, the Data Fabric= on the GPU nodes can be accessed the same way as the Data Fabric on CPU no= des. > Aldebaran GPUs have 2 root ports, with 4 misc port for each root. >=20 I don't fully understand this sentence. There are 2 "Nodes"/Data Fabrics pe= r GPU package, but what do "4 misc port for each root" mean? In any case, i= s this relevant to this patch? Also, there should be an imperitive in the commit message, i.e. "Add ...". [naveenk:] Modified the commit message > Signed-off-by: Muralidhara M K > Signed-off-by: Naveen Krishna Chatradhi > --- > arch/x86/include/asm/amd_nb.h | 6 ++++ > arch/x86/kernel/amd_nb.c | 62 ++++++++++++++++++++++++++++++++--- > 2 files changed, 63 insertions(+), 5 deletions(-) >=20 > diff --git a/arch/x86/include/asm/amd_nb.h=20 > b/arch/x86/include/asm/amd_nb.h index 00d1a400b7a1..e71581cf00e3=20 > 100644 > --- a/arch/x86/include/asm/amd_nb.h > +++ b/arch/x86/include/asm/amd_nb.h > @@ -79,6 +79,12 @@ struct amd_northbridge_info { > =20 > #ifdef CONFIG_AMD_NB > =20 > +/* > + * On Newer heterogeneous systems from AMD with CPU and GPU nodes=20 > +connected > + * via xGMI links, the NON CPU Nodes are enumerated from index 8 */ > +#define NONCPU_NODE_INDEX 8 "Newer" doesn't need to be capatilized. And there should be a period at the= end of the sentence. I don't think "xGMI links" would mean much to most folks. I think the impli= cation here is that the CPUs and GPUs are connected directly together (or r= ather their Data Fabrics are connected) like is done with 2 socket CPU systems and also within a socket for Multi-chip Module (MCM) CPUs like Naples. [naveenk:] Modified the message > + > u16 amd_nb_num(void); > bool amd_nb_has_feature(unsigned int feature); struct=20 > amd_northbridge *node_to_amd_nb(int node); diff --git=20 > a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index=20 > 5884dfa619ff..489003e850dd 100644 > --- a/arch/x86/kernel/amd_nb.c > +++ b/arch/x86/kernel/amd_nb.c > @@ -26,6 +26,8 @@ > #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444 > #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654 > #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e > +#define PCI_DEVICE_ID_AMD_ALDEBARAN_ROOT 0x14bb > +#define PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F4 0x14d4 > These PCI IDs look correct. > /* Protect the PCI config register pairs used for SMN. */ static=20 > DEFINE_MUTEX(smn_mutex); @@ -94,6 +96,21 @@ static const struct=20 > pci_device_id hygon_nb_link_ids[] =3D { > {} > }; > =20 > +static const struct pci_device_id amd_noncpu_root_ids[] =3D { > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ALDEBARAN_ROOT) }, > + {} > +}; > + > +static const struct pci_device_id amd_noncpu_nb_misc_ids[] =3D { > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F3) }, > + {} > +}; > + > +static const struct pci_device_id amd_noncpu_nb_link_ids[] =3D { > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F4) }, > + {} > +}; > + I think separating the CPU and non-CPU IDs is a good idea. > const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = =3D { > { 0x00, 0x18, 0x20 }, > { 0xff, 0x00, 0x20 }, > @@ -182,11 +199,16 @@ int amd_cache_northbridges(void) > const struct pci_device_id *misc_ids =3D amd_nb_misc_ids; > const struct pci_device_id *link_ids =3D amd_nb_link_ids; > const struct pci_device_id *root_ids =3D amd_root_ids; > + > + const struct pci_device_id *noncpu_misc_ids =3D amd_noncpu_nb_misc_ids; > + const struct pci_device_id *noncpu_link_ids =3D amd_noncpu_nb_link_ids; > + const struct pci_device_id *noncpu_root_ids =3D amd_noncpu_root_ids; > + > struct pci_dev *root, *misc, *link; > struct amd_northbridge *nb; > u16 roots_per_misc =3D 0; > - u16 misc_count =3D 0; > - u16 root_count =3D 0; > + u16 misc_count =3D 0, misc_count_noncpu =3D 0; > + u16 root_count =3D 0, root_count_noncpu =3D 0; > u16 i, j; > =20 > if (amd_northbridges.num) > @@ -205,10 +227,16 @@ int amd_cache_northbridges(void) > if (!misc_count) > return -ENODEV; > =20 > + while ((misc =3D next_northbridge(misc, noncpu_misc_ids)) !=3D NULL) > + misc_count_noncpu++; > + > root =3D NULL; > while ((root =3D next_northbridge(root, root_ids)) !=3D NULL) > root_count++; > =20 > + while ((root =3D next_northbridge(root, noncpu_root_ids)) !=3D NULL) > + root_count_noncpu++; > + > if (root_count) { > roots_per_misc =3D root_count / misc_count; > =20 > @@ -222,15 +250,27 @@ int amd_cache_northbridges(void) > } > } > =20 > - nb =3D kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL); > + /* > + * The valid amd_northbridges are in between (0 ~ misc_count) and > + * (NONCPU_NODE_INDEX ~ NONCPU_NODE_INDEX + misc_count_noncpu) > + */ This comment isn't clear to me. Is it even necessary? [naveenk:] moved the message > + if (misc_count_noncpu) > + /* > + * There are NONCPU Nodes with pci root ports starting at index 8 > + * allocate few extra cells for simplicity in handling the indexes > + */ I think this comment can be more explicit. The first non-CPU Node ID starts= at 8 even if there are fewer than 8 CPU nodes. To maintain the AMD Node ID= to Linux amd_nb indexing scheme, allocate the number of GPU nodes plus 8. = Some allocated amd_northbridge structures will go unused when the number of= CPU nodes is less than 8, but this tradeoff is to keep things relatively s= imple. > + amd_northbridges.num =3D NONCPU_NODE_INDEX + misc_count_noncpu; > + else > + amd_northbridges.num =3D misc_count; The if-else statements should have {}s even though there's only a single li= ne of code in each. This is just to make it easier to read multiple lines. = Or the second code comment can be merged with the first outside the if-else= . [naveenk:] Done > + > + nb =3D kcalloc(amd_northbridges.num, sizeof(struct amd_northbridge),=20 > +GFP_KERNEL); > if (!nb) > return -ENOMEM; > =20 > amd_northbridges.nb =3D nb; > - amd_northbridges.num =3D misc_count; > =20 > link =3D misc =3D root =3D NULL; > - for (i =3D 0; i < amd_northbridges.num; i++) { > + for (i =3D 0; i < misc_count; i++) { > node_to_amd_nb(i)->root =3D root =3D > next_northbridge(root, root_ids); > node_to_amd_nb(i)->misc =3D misc =3D > @@ -251,6 +291,18 @@ int amd_cache_northbridges(void) > root =3D next_northbridge(root, root_ids); > } > =20 > + link =3D misc =3D root =3D NULL; This line can go inside the if statement below. [naveenk:] Done I'm not sure it's totally necessary since the GPU devices should be listed = after the CPU devices. But I guess better safe than sorry in case that impl= ementation detail doesn't hold in the future. If you keep it, then I think = you should do the same above when finding the counts. > + if (misc_count_noncpu) { > + for (i =3D NONCPU_NODE_INDEX; i < NONCPU_NODE_INDEX + misc_count_noncp= u; i++) { > + node_to_amd_nb(i)->root =3D root =3D > + next_northbridge(root, noncpu_root_ids); > + node_to_amd_nb(i)->misc =3D misc =3D > + next_northbridge(misc, noncpu_misc_ids); > + node_to_amd_nb(i)->link =3D link =3D > + next_northbridge(link, noncpu_link_ids); > + } > + } > + > if (amd_gart_present()) > amd_northbridges.flags |=3D AMD_NB_GART; > =20 > -- Thanks, Yazen [naveenk:] Than you