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Wed, 10 Jul 2019 00:51:46 +0000 From: Tyler Baicar OS To: James Morse CC: Open Source Submission , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-edac@vger.kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "lorenzo.pieralisi@arm.com" , "guohanjun@huawei.com" , "sudeep.holla@arm.com" , "rjw@rjwysocki.net" , "lenb@kernel.org" , "mark.rutland@arm.com" , "tony.luck@intel.com" , "bp@alien8.de" , "Matteo.Carlini@arm.com" , "Andrew.Murray@arm.com" Subject: Re: [PATCH RFC 2/4] arm64: mm: Add RAS extension system register check to SEA handling Thread-Topic: [PATCH RFC 2/4] arm64: mm: Add RAS extension system register check to SEA handling Thread-Index: AQHVMPZvV84yhcAYOk+DNBn1Cdw2C6bAhfiAgAKLP64= Date: Wed, 10 Jul 2019 00:51:46 +0000 Message-ID: References: <1562086280-5351-1-git-send-email-baicar@os.amperecomputing.com> <1562086280-5351-3-git-send-email-baicar@os.amperecomputing.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=baicar@os.amperecomputing.com; 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received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: fuXocvV0pWjEYBY40KX1ca3xre+GTKWzh4K20ho3PAsOCf1w6at7aBxLrmQBp7S+HPzCVIQcHj5LeMYT6jyg9Ow2ohYr0Z6FPYF4EpSAd3LquHO526RPojFh2SisZKdpONGjabaPuVF5zgi0Kb29y9wrTZyfLjxleQmtPCu7J9RZAmb+cP0SDY32fihTDglAPRBZitSFgQcyUk/7Icwwf8KFD8w7eYJHLKp8vaiSUrdZStVP1jkKIux4PuM4OQfyHiG4QrRi3+s2NqlQD40KQYotqyj+XlFJLUWXhG3TYCJ85IYodm53TP/1GquvuScuLo683t4+RwH05HXDXuLscFJ8q2nXUpN6WcKB1DL926DtQpVokkQjFjiX3NSW3EwxT72YBG7Z7bYHWftDvZI215IOx44tKQPT2eEzvQppKuw= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 25ea764d-2bad-4627-5263-08d704d0c91b X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 00:51:46.8664 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Baicar@os.amperecomputing.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR01MB4790 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On Mon, Jul 8, 2019 at 10:10 AM James Morse wrote: > On 02/07/2019 17:51, Tyler Baicar OS wrote: > > On systems that support the ARM RAS extension, synchronous external > > abort syndrome information could be captured in the core's RAS extensio= n > > system registers. So, when handling SEAs check the RAS system registers > > for error syndrome information. > > > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c > > index 2d11501..76b42ca 100644 > > --- a/arch/arm64/mm/fault.c > > +++ b/arch/arm64/mm/fault.c > > @@ -37,6 +37,7 @@ > > #include > > #include > > #include > > +#include > >=20 > > struct fault_info { > > int (*fn)(unsigned long addr, unsigned int esr, > > @@ -632,6 +633,8 @@ static int do_sea(unsigned long addr, unsigned int = esr, struct pt_regs *regs) > >=20 > > inf =3D esr_to_fault_info(esr); > >=20 > > + arch_arm_ras_report_error(); > > + > > /* > > * Return value ignored as we rely on signal merging. > > * Future patches will make this more robust. > > > > If we interrupted a preemptible context, do_sea() is preemptible too... T= his means we > can't know if we're still running on the same CPU as the one that took th= e external-abort. > (until this series, it hasn't mattered). > > Fixing this means cramming something into entry.S's el1_da, as this may u= nmask interrupts > before calling do_mem_abort(). But its going to be ugly because some of d= o_mem_abort()s > ESR values need to be preemptible because they sleep, e.g. page-faults ca= lling > handle_mm_fault(). > For do_sea(), do_exit() will 'fix' the preempt count if we kill the threa= d, but if we > don't, it still needs to be balanced. Doing all this in assembly is going= to be unreadable! > > Mark Rutland has a series to move the entry assembly into C [0]. Based on= that that it > should be possible for the new el1_abort() to spot a Synchronous-External= -Abort ESR, and > wrap the do_mem_abort() with preempt enable/disable, before inheriting th= e flags. (which > for synchronous exceptions, I think we should always do) > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/log/?h= =3Darm64/entry-deasm Hey James, Good catch! I didn't think the synchronous route was preemptible. I wasn't seeing this issue when testing this on emulation, but I was able t= o test and prove the issue on a Neoverse N1 SDP: root@genericarmv8:~# echo 0x100000000 > /proc/cached_read [ 42.985622] Reading from address 0x100000000 [ 42.989893] WARNING: CPU: 0 PID: 2812 at /home/tyler/neoverse/arm-refere= nce- platforms/linux/arch/arm64/kernel/cpufeature.c:1940 this_cpu_has_cap+0x68/0= x78 [..] [ 43.119083] Call trace: [ 43.121515] this_cpu_has_cap+0x68/0x78 [ 43.125338] do_sea+0x34/0x70 [ 43.128292] do_mem_abort+0x3c/0x98 [ 43.131765] el1_da+0x20/0x94 [ 43.134722] cached_read+0x30/0x68 [ 43.138112] simple_attr_write+0xbc/0x128 [ 43.142109] proc_reg_write+0x60/0xa8 [ 43.145757] __vfs_write+0x18/0x40 [ 43.149145] vfs_write+0xa4/0x1b8 [ 43.152445] ksys_write+0x64/0xe0 [ 43.155746] __arm64_sys_write+0x14/0x20 [ 43.159654] el0_svc_common.constprop.0+0xa8/0x100 [ 43.164430] el0_svc_handler+0x28/0x78 [ 43.168165] el0_svc+0x8/0xc [ 43.171031] ---[ end trace 2c27619659261a1d ]--- [ 43.175647] Internal error: synchronous external abort: 96000410 [#1] PREEMPT SMP [..] That warning is because it's preemptible: if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { I'll pull Mark's series in and add the preempt enable/disable around the ca= ll to do_mem_abort() in el1_abort() and test that out! Thanks, Tyler=