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From: Tony Luck <tony.luck@intel.com>
To: Jiping Ma <jiping.ma2@windriver.com>
Cc: Jason Baron <jbaron@akamai.com>,
	Linux Edac Mailing List <linux-edac@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Borislav Petkov <bp@alien8.de>
Subject: Re: [PATCH] EDAC, ie31200: Add Intel Corporation 3rd Gen Core processor
Date: Mon, 12 Aug 2019 10:16:40 -0700
Message-ID: <CA+8MBbKegE2Z3YqB+a4XFEwN=C23YG3c9ju3su-WS5pt1HPCwA@mail.gmail.com> (raw)
In-Reply-To: <1560928518-243100-2-git-send-email-jiping.ma2@windriver.com>

On Wed, Jun 19, 2019 at 12:34 AM Jiping Ma <jiping.ma2@windriver.com> wrote:

Oops. Boris pointed out to me that this has been left hanging. Sorry
for the delay.

> 3rd Gen Core seems to work just like Skylake.

Maybe "just like all the other Xeon-E3 processors?

"3rd Gen Core" seems to be Ivybridge generation (based on the PCI
device ID below).
I.e. "Xeon E3-12xx V2". Is that correct?

I don't have a way to test that, so I'd like some more details on the
testing that
you have done.  Specifically has this driver been run on a system and correctly
reported at least one error?

> Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
> ---
>  drivers/edac/ie31200_edac.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
> index aac9b9b..1445336 100644
> --- a/drivers/edac/ie31200_edac.c
> +++ b/drivers/edac/ie31200_edac.c
> @@ -19,6 +19,7 @@
>   * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
>   * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
>   * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
> + * 0154: 3rd Gen Core processor DRAM Controller

I think this line should be added chronologically by age of processor
(i.e. at the start
of the list)

>   *
>   * Based on Intel specification:
>   * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
> @@ -59,6 +60,7 @@
>  #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
>  #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
>  #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x0154
>
>  #define IE31200_DIMMS                  4
>  #define IE31200_RANKS                  8
> @@ -569,6 +571,9 @@ static void ie31200_remove_one(struct pci_dev *pdev)
>                 PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
>                 IE31200},
>         {
> +               PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0
> +               , IE31200},
> +       {
>                 0,
>         }            /* 0 terminated list. */
>  };
> --
> 1.9.1
>

      reply index

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-19  7:15 Review request for edac: " Jiping Ma
2019-06-19  7:15 ` [PATCH] EDAC, " Jiping Ma
2019-08-12 17:16   ` Tony Luck [this message]

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