Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc

Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc

[Christoph Hellwig]

On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > ---
> >  arch/riscv/mm/Makefile                            | 1 -
> >  drivers/misc/Makefile                             | 1 +
> >  {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> >  3 files changed, 1 insertion(+), 1 deletion(-)
> >  rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
> 
> Why isn't this in drivers/edac/ ?
> why is this a misc driver?  Seems like it should sit next to the edac
> stuff.

No idea.  EDAC maintainers, would you object to taking what is 
currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?

Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc

[Paul Walmsley]

On Wed, 7 Aug 2019, Christoph Hellwig wrote:

> On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> > > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > > ---
> > >  arch/riscv/mm/Makefile                            | 1 -
> > >  drivers/misc/Makefile                             | 1 +
> > >  {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> > >  3 files changed, 1 insertion(+), 1 deletion(-)
> > >  rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
> > 
> > Why isn't this in drivers/edac/ ?
> > why is this a misc driver?  Seems like it should sit next to the edac
> > stuff.
> 
> No idea.  EDAC maintainers, would you object to taking what is 
> currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?

If this driver is moved out of arch/riscv/mm, it should ideally go into 
some sort of common L2 cache controller driver directory, along 
with other L2 cache controller drivers like arch/arm/mm/*l2c*. 

Like many L2 cache controllers, this controller also supports cache 
flushing operations and SoC-specific way operations.  We just don't use 
those on RISC-V - yet.


- Paul

Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc

[Christoph Hellwig]

On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote:
> On Wed, 7 Aug 2019, Christoph Hellwig wrote:
> 
> > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> > > > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > > > ---
> > > >  arch/riscv/mm/Makefile                            | 1 -
> > > >  drivers/misc/Makefile                             | 1 +
> > > >  {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> > > >  3 files changed, 1 insertion(+), 1 deletion(-)
> > > >  rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
> > > 
> > > Why isn't this in drivers/edac/ ?
> > > why is this a misc driver?  Seems like it should sit next to the edac
> > > stuff.
> > 
> > No idea.  EDAC maintainers, would you object to taking what is 
> > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?
> 
> If this driver is moved out of arch/riscv/mm, it should ideally go into 
> some sort of common L2 cache controller driver directory, along 
> with other L2 cache controller drivers like arch/arm/mm/*l2c*. 
> 
> Like many L2 cache controllers, this controller also supports cache 
> flushing operations and SoC-specific way operations.  We just don't use 
> those on RISC-V - yet.

Well, another reason to not have it under arch/riscv/ as it is a SOC
specific driver, which we all have somewhere else, just like arm64
and new arm ports do.  And especially not unconditionally built.

Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc

[Arnd Bergmann]

On Thu, Aug 8, 2019 at 9:50 AM Christoph Hellwig <hch@lst.de> wrote:
> On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote:
> > On Wed, 7 Aug 2019, Christoph Hellwig wrote:
> > > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> > > > > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > > > > ---
> > > > >  arch/riscv/mm/Makefile                            | 1 -
> > > > >  drivers/misc/Makefile                             | 1 +
> > > > >  {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> > > > >  3 files changed, 1 insertion(+), 1 deletion(-)
> > > > >  rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
> > > >
> > > > Why isn't this in drivers/edac/ ?
> > > > why is this a misc driver?  Seems like it should sit next to the edac
> > > > stuff.
> > >
> > > No idea.  EDAC maintainers, would you object to taking what is
> > > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?
> >
> > If this driver is moved out of arch/riscv/mm, it should ideally go into
> > some sort of common L2 cache controller driver directory, along
> > with other L2 cache controller drivers like arch/arm/mm/*l2c*.
> >
> > Like many L2 cache controllers, this controller also supports cache
> > flushing operations and SoC-specific way operations.  We just don't use
> > those on RISC-V - yet.
>
> Well, another reason to not have it under arch/riscv/ as it is a SOC
> specific driver, which we all have somewhere else, just like arm64
> and new arm ports do.  And especially not unconditionally built.

soc specific drivers that don't have their own subsystem can
go into drivers/soc/$VENDOR/.

For this driver, I would also think that the edac subsystem is the
best fit. Right now, the driver is split in two halves: there
is drivers/edac/sifive_edac.c and arch/riscv/mm/sifive_l2_cache.c,
with neither of those working without the other.

Moving both into a single file would seem to allow simplifying
it as a proper 'platform_driver', which the drivers/edac side today
is not (it just registers a platform device in its module_init call).

      Arnd