From: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 1/8] EDAC/amd64: Fix number of DIMMs and Chip Select bases/masks on Family17h
Date: Thu, 13 Jun 2019 21:00:19 +0000 [thread overview]
Message-ID: <SN6PR12MB263988EC0AC99DA2D29B21F3F8EF0@SN6PR12MB2639.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20190613135822.GC11598@zn.tnic>
> -----Original Message-----
> From: Borislav Petkov <bp@alien8.de>
> Sent: Thursday, June 13, 2019 8:58 AM
> To: Ghannam, Yazen <Yazen.Ghannam@amd.com>
> Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 1/8] EDAC/amd64: Fix number of DIMMs and Chip Select bases/masks on Family17h
>
> On Fri, May 31, 2019 at 11:45:11PM +0000, Ghannam, Yazen wrote:
> > From: Yazen Ghannam <yazen.ghannam@amd.com>
> >
> > ...because AMD Family 17h systems support 2 DIMMs, 4 CS bases, and 2 CS
> > masks per channel.
> >
> > Fixes: 07ed82ef93d6 ("EDAC, amd64: Add Fam17h debug output")
> > Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> > ---
> > drivers/edac/amd64_edac.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> > index 873437be86d9..9fa2f205f05c 100644
> > --- a/drivers/edac/amd64_edac.c
> > +++ b/drivers/edac/amd64_edac.c
> > @@ -810,7 +810,7 @@ static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl)
> >
> > edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);
> >
> > - for (dimm = 0; dimm < 4; dimm++) {
> > + for (dimm = 0; dimm < 2; dimm++) {
> > size0 = 0;
> > cs0 = dimm * 2;
> >
> > @@ -942,6 +942,9 @@ static void prep_chip_selects(struct amd64_pvt *pvt)
> > } else if (pvt->fam == 0x15 && pvt->model == 0x30) {
> > pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
> > pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
> > + } else if (pvt->fam >= 0x17) {
> > + pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
> > + pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
>
> I guess it is about time that function gets turned into a switch-case so
> that the assignment lines do not get duplicated.
>
Okay, I'll write up a patch for that.
Do you have any tips on how to handle it? I'm thinking it may be tricky because of the ranges and multiple variables.
Thanks,
Yazen
next prev parent reply other threads:[~2019-06-13 21:00 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-31 23:45 [PATCH 0/8] AMD64 EDAC fixes for v5.2 Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 1/8] EDAC/amd64: Fix number of DIMMs and Chip Select bases/masks on Family17h Ghannam, Yazen
2019-06-13 13:58 ` Borislav Petkov
2019-06-13 21:00 ` Ghannam, Yazen [this message]
2019-06-17 13:37 ` Borislav Petkov
2019-05-31 23:45 ` [PATCH 2/8] EDAC/amd64: Support more than two controllers for chip selects handling Ghannam, Yazen
2019-06-13 14:17 ` Borislav Petkov
2019-06-13 20:58 ` Ghannam, Yazen
2019-06-13 22:22 ` Borislav Petkov
2019-06-14 14:14 ` Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 3/8] EDAC/amd64: Recognize DRAM device type with EDAC_CTL_CAP Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 5/8] EDAC/amd64: Find Chip Select memory size using Address Mask Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 4/8] EDAC/amd64: Initialize DIMM info for systems with more than two channels Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 7/8] EDAC/amd64: Cache secondary Chip Select registers Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 6/8] EDAC/amd64: Decode syndrome before translating address Ghannam, Yazen
2019-05-31 23:45 ` [PATCH 8/8] EDAC/amd64: Support Asymmetric Dual-Rank DIMMs Ghannam, Yazen
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