From: Alison Wang <alison.wang@nxp.com>
To: James Morse <james.morse@arm.com>, "bp@alien8.de" <bp@alien8.de>,
"tony.luck@intel.com" <tony.luck@intel.com>
Cc: "mchehab@kernel.org" <mchehab@kernel.org>,
"rrichter@marvell.com" <rrichter@marvell.com>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [EXT] Re: [PATCH] edac: nxp: Add L1 and L2 error detection for A53 and A72 cores
Date: Tue, 25 Aug 2020 02:31:09 +0000 [thread overview]
Message-ID: <VI1PR04MB4062A3BF31A7002AD45E5200F4570@VI1PR04MB4062.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <92811e33-2f57-244b-4b50-c2831b09b835@arm.com>
Hi, James,
> On 09/07/2020 09:22, Alison Wang wrote:
> > Add error detection for A53 and A72 cores. Hardware error injection is
> > supported on A53. Software error injection is supported on both.
>
<snip>
>
> As we can't safely write to these registers from linux, so I think this means all
> the error injection and maybe SMC stuff can disappear.
>
>
> (I've not read past here..)
>
[Alison] Thank you very much for all your detailed comments.
I agreed with your opinion that CPUACTLR_EL1 and L2ACTLR can't be written in Linux. So the error injection can't be done in Linux. Do you mean the error injection can only be done in firmware before Linux boots up? If so, the system is running with error injection enabled all the time, it may be not a good idea too. Any suggestion?
Best Regards,
Alison Wang
next prev parent reply other threads:[~2020-08-25 2:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-09 8:22 [PATCH] edac: nxp: Add L1 and L2 error detection for A53 and A72 cores Alison Wang
2020-08-15 8:41 ` Borislav Petkov
2020-08-21 11:38 ` James Morse
2020-08-25 2:31 ` Alison Wang [this message]
2020-08-25 13:18 ` [EXT] " James Morse
2020-08-26 3:03 ` Alison Wang
2020-08-27 10:40 ` Borislav Petkov
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