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Wed, 10 Jul 2019 16:54:45 +0000 From: "Phillips, Kim" To: "Ghannam, Yazen" , "linux-edac@vger.kernel.org" CC: "linux-kernel@vger.kernel.org" , "bp@alien8.de" Subject: Re: [PATCH v2 1/7] EDAC/amd64: Support more than two controllers for chip selects handling Thread-Topic: [PATCH v2 1/7] EDAC/amd64: Support more than two controllers for chip selects handling Thread-Index: AQHVN0Asc2CazzfP60GUzjiUo3pGLA== Date: Wed, 10 Jul 2019 16:54:44 +0000 Message-ID: References: <20190709215643.171078-1-Yazen.Ghannam@amd.com> <20190709215643.171078-2-Yazen.Ghannam@amd.com> In-Reply-To: <20190709215643.171078-2-Yazen.Ghannam@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR2101CA0017.namprd21.prod.outlook.com (2603:10b6:805:106::27) To MWHPR12MB1806.namprd12.prod.outlook.com (2603:10b6:300:10d::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=kim.phillips@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.77.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9ede45b6-e7f9-4a75-9786-08d705574f45 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:MWHPR12MB1758; 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charset="Windows-1252" Content-ID: <5B6D0F510AADE5429747A14E82A53C05@namprd12.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9ede45b6-e7f9-4a75-9786-08d705574f45 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 16:54:44.8840 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: kphillips@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1758 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On 7/9/19 4:56 PM, Ghannam, Yazen wrote: > From: Yazen Ghannam >=20 > The struct chip_select array that's used for saving chip select bases > and masks is fixed at length of two. There should be one struct > chip_select for each controller, so this array should be increased to > support systems that may have more than two controllers. >=20 > Increase the size of the struct chip_select array to eight, which is the > largest number of controllers per die currently supported on AMD > systems. >=20 > Fix number of DIMMs and Chip Select bases/masks on Family17h, because AMD > Family 17h systems support 2 DIMMs, 4 CS bases, and 2 CS masks per > channel. >=20 > Also, carve out the Family 17h+ reading of the bases/masks into a > separate function. This effectively reverts the original bases/masks > reading code to before Family 17h support was added. >=20 > This is a second version of a commit that was reverted. >=20 > Fixes: 07ed82ef93d6 ("EDAC, amd64: Add Fam17h debug output") > Fixes: 8de9930a4618 ("Revert "EDAC/amd64: Support more than two controlle= rs for chip select handling"") > Signed-off-by: Yazen Ghannam > --- For this and the rest of the series: Tested-by: Kim Phillips Thanks, Kim