Linux-EDAC Archive on lore.kernel.org
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From: Shiping Ji <shiping.linux@gmail.com>
To: bp@alien8.de, james.morse@arm.com, robh+dt@kernel.org,
	mark.rutland@arm.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	mchehab@kernel.org, linux-edac@vger.kernel.org,
	sashal@kernel.org, hangl@microsoft.com, lewan@microsoft.com,
	ruizhao@microsoft.com, scott.branden@broadcom.com,
	yuqing.shen@broadcom.com, ray.jui@broadcom.com,
	shji@microsoft.com, wangglei@gmail.com
Subject: [PATCH v7 1/2] dt-bindings: edac: arm-dmc520.txt
Date: Sun, 17 Nov 2019 18:10:43 -0800
Message-ID: <f947d821-8e67-dcc7-d753-5b04d099792d@gmail.com> (raw)

This is the device tree bindings for new EDAC driver dmc520_edac.c.

Signed-off-by: Lei Wang <leiwang_git@outlook.com>
Reviewed-by: James Morse <james.morse@arm.com>

---
     Changes in v7:
         - Added arm prefix to the interrupt-config property

---
 .../devicetree/bindings/edac/arm-dmc520.txt   | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/edac/arm-dmc520.txt

diff --git a/Documentation/devicetree/bindings/edac/arm-dmc520.txt b/Documentation/devicetree/bindings/edac/arm-dmc520.txt
new file mode 100644
index 000000000000..476cf8b76f2a
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/arm-dmc520.txt
@@ -0,0 +1,26 @@
+* ARM DMC-520 EDAC node
+
+Required properties:
+- compatible  : "brcm,dmc-520", "arm,dmc-520".
+- reg   : Address range of the DMC-520 registers.
+- interrupts  : DMC-520 interrupt numbers. The example below specifies
+     two interrupt lines for dram_ecc_errc_int and
+     dram_ecc_errd_int.
+- arm,interrupt-config : This is an array of interrupt masks. For each of the
+     above interrupt line, add one interrupt mask element to
+     it. That is, there is a 1:1 mapping from each interrupt
+     line to an interrupt mask. An interrupt mask can represent
+     multiple interrupts being enabled. Refer to interrupt_control
+     register in DMC-520 TRM for interrupt mapping. In the example
+     below, the interrupt configuration enables dram_ecc_errc_int
+     and dram_ecc_errd_int. And each interrupt is connected to
+     a separate interrupt line.
+
+Example:
+
+dmc0: dmc@200000 {
+ compatible = "brcm,dmc-520", "arm,dmc-520";
+ reg = <0x200000 0x80000>;
+ interrupts = <0x0 0x349 0x4>, <0x0 0x34B 0x4>;
+ arm,interrupt-config = <0x4>, <0x8>;
+};
-- 
2.17.1


             reply index

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-18  2:10 Shiping Ji [this message]
2019-11-21 20:43 ` Rob Herring
2019-12-03 22:04   ` Shiping Ji
2019-12-17 22:51 ` Yuqing Shen

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