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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id s125sm15564588pfb.125.2020.08.25.09.02.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 09:02:51 -0700 (PDT) Date: Tue, 25 Aug 2020 09:02:51 -0700 (PDT) X-Google-Original-Date: Tue, 25 Aug 2020 08:24:30 PDT (-0700) Subject: Re: [PATCH 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs In-Reply-To: <1598357182-4226-2-git-send-email-yash.shah@sifive.com> CC: robh+dt@kernel.org, Paul Walmsley , bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, aou@eecs.berkeley.edu, james.morse@arm.com, rrichter@marvell.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, sachin.ghadi@sifive.com, yash.shah@sifive.com From: Palmer Dabbelt To: yash.shah@sifive.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On Tue, 25 Aug 2020 05:06:20 PDT (-0700), yash.shah@sifive.com wrote: > Add device tree bindings for SiFive FU540 DDR controller driver > > Signed-off-by: Yash Shah > --- > .../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml > new file mode 100644 > index 0000000..0288119 > --- /dev/null > +++ b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml > @@ -0,0 +1,41 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/riscv/sifive-ddr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive DDR memory controller binding > + > +description: | > + The Sifive DDR controller driver is used to manage the Cadence DDR > + controller present in SiFive FU540-C000 SoC. Currently the driver is > + used to manage EDAC feature of the DDR controller. > + > +maintainers: > + - Yash Shah > + > +properties: > + compatible: > + enum: > + - sifive,fu540-c000-ddr > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + memory-controller@100b0000 { > + compatible = "sifive,fu540-c000-ddr"; > + reg = <0x100b0000 0x4000>; > + interrupts = <31>; > + }; Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt